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Original question:

UC2854: Loop Compensation in UC2854

UC2854: Loop Compensation and Current Limit

Ravichandra badiger
Prodigy 10 points
Part Number: UC2854

Tool/software:

In the loop compensation of the UC2854 IC, is there any relation between the loop compensation pin (Pin 7) and the PKLMT pin (Pin 2)? Specifically, is there any relation between the voltage loop compensation and the current limit?

Also, please explain the concept of offset voltage in the PKLMT pin. How does it vary with the capacitor connected to it? For example, we observed an offset voltage of about 30 mV when using a 100 nF capacitor. Please provide any correlated data showing the variation of offset voltage with respect to different capacitor values in this IC. The datasheet specifies a range of –15 mV to +15 mV, but we are seeing different values depending on the capacitor used.

  • 0
    TI__Mastermind 40350 points

    Hello Ravichandra, 

    There is no correlation between the voltage loop compensation and the PKLMT or current limit.  

    The PKLMT offset voltage is simply the offset voltage of the PKLMT comparator's negative input with respect to the positive input. 

    The UC2854 datasheet indicates +/-10mV max (not +/-15mV):

    This offset is simply the input voltage necessary at PKLMT that is required to toggle the comparator output from low to high.
    Normally, the voltage at PKLMT is positive with respect to IC GND (pin 1), so the comparator output is low and the PWM flipflop is not reset by PKLMT.   
    Excessive current through Rsense (the current sense resistor) will pull PKLMT below GND to toggle the comparator and reset the PWM FF.  
    +/-10mV offset means that PKLMT voltage can be as high as +10mV or as low as -10mV with respect to GND to toggle the output. 
    But these are the guaranteed extreme limits and usually the true offset is much closer to 0mV. 

    A capacitor attached to PKLMT has no effect on the offset voltage.  A DC voltage applied to PKLMT would prove that. 

    However, the Rsense current has an AC ripple content and the PKLMT capacitor filters this AC ripple.
    The ripple is superimposed on the DC level at PKLMT and triggers current limit when 0V is crossed. 

    A large value will attenuate the ripple more than a low value, so it may appear that different different caps cause a different offset voltage. 
    That is not the case.  Different caps cause differing ripple amplitudes so the apparent trip point varies. 

    Note: large values for filter caps on PKLMT will reduce the AC ripple on the signal, but will also introduce a time-delay for triggering the PKLMT.
    To maintain reasonable cycle-by-cycle response at PKLMT, I suggest to avoid designing an R-C time constant that exceeds a few hundred nanoseconds.

    Regards,
    Ulrich