Tool/software:
Hello,
I am working with a BQ27Z758YAHR configured with two external NFETs EFC2J013NUZ (back-to-back, common-drain). The circuit is essentially the same as the reference schematic in the datasheet (around page 24).
Test conditions and observations
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Battery: single cell, 3.95 V, 1500 mAh
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PACK: powered from a bench supply set to 4.2 V, current limited (no load observed)
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BAT_SP = 3.57 V, BAT_SN = 0.00 V
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DSG = 3.74 V with PACK = 4.2 V → the gate is below PACK (so NFETs remain OFF)
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CHG: not measured in this setup
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VDD = 3.95 V, BAT = 3.95 V
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ENAB = 3.57 V (also tried forcing it low, no improvement)
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TS: ~8 ms pulses at ~612 mV (seems normal)
In these conditions, the external FETs remain OFF (PACK+ is isolated from BAT+).
I²C note
At the moment, I have not implemented I²C communication. The SDA and SCL lines are at 0 V (no pull-ups installed). I am wondering if the absence of I²C/pull-ups could itself prevent the FETs from being enabled, or if I²C is only required to read/clear possible latched faults.
I am attaching the schematic and layout in case I have overlooked something.
Thank you for any suggestions!
— Giulio Montanari
