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TPS7B63-Q1: Pin FMA : PGADJ OPEN

rui saito
Prodigy 250 points
Part Number: TPS7B63-Q1

Tool/software:

Hi team

Since the behavior of pin FMA of the TPS7B63-Q1 when PGADJ = OPEN was not described, I checked it on an actual device.

The conclusion was that the voltage was always at GND level, and the waveform appeared to be pulled down internally by the IC.

However, even after looking at the datasheet, I could not understand why this waveform appeared.

Please explain why PGADJ is at GND level voltage when it is OPEN.

Best regards,

Saito

  • 0
    TI__Prodigy 735 points

    Hi Rui

    Great question. The PG pin is OPEN because the PG pin is an open-drain output with an external pulldown resistor to regulate supply. Connecting PGADJ to GND sets the PG threshold value to the default. Section 6.3.2 in the DS shows the typical hardware connections for PGADJ and DELAY pin

    Thanks,

    Suchit