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TPS536C9T: Pin connection and PCB layout for TPS536C9T

Adhistira Naradhipa
Prodigy 20 points
Part Number: TPS536C9T
Other Parts Discussed in Thread: TPS536C7EVM-051

Tool/software:

Hi,

I’m working on building an evaluation board using the TPS536C9T for a twelve-phase TLVR system, with both an electronic load and a load slammer for transient testing. While reviewing the datasheet, I couldn’t find clear guidance on how to connect the following pins:

  1. Pin 19: SYNC / RESET# / PIN_ALERT# / PSYS_CRIT#

  2. Pin 44: ATSEN / BTSEN / ISYS_IN

The sample application from the datasheet is intended for CPU load, where communication between the CPU and the TPS536C9T exists.

In addition, are there any available documents or application notes on best layout practices for the TPS536C9T? Currently, I’m referencing the layout from the TPS536C7EVM-051, but having more detailed documentation or guidance would be extremely helpful, especially for PCB layout considerations.

Any pointers, documentation, or contacts who could provide support would be greatly appreciated.

Thank you!

Adhis

  • 0
    TI__Prodigy 110 points

    Hi Adhis,

    For pin 19 since you aren't using a CPU you can set up:

    -Reset#: Set to pull up resistor

    For pin 44 you can set it to the temperature pin of the rail you are not using.

    Some good layout practices for this controller I found are:

    1. keep at a minimum 800mil distance between controller and all power stages

    2. Have controller and Power stages on common ground plane

    3. Keep PWMx routed on a different quiet inner layer away from CSPX or VREF differential pairs.

    4.Bypass capacitors connected to VCC,VREF, VS_CSNIN, and CSPIN you should place close to the controller pin on the same layer

    5. For current source IMON power stages try to avoid any noise sources nearby

    Hope this helps,

    -Will