Tool/software:
Hi,
What's the best PCB stack-up, especially as my current sense pair of tracks will run a long way around?
If i have 2 PGND layers with current sense pair sandwiched between them (and a few other signals), would the bottom layer only be connected to any PGND connection that needs a thermal connection and nothing else?
This says analog ground... "Add several vias under EP to help conduct heat away from the device. Connect the vias to a large analog ground plane on the bottom layer."
So would a thermal connection from the bottom FET PGND need to be to a different polygon?
In the datasheet, section 11.2 layout example it looks like the bottom layer isn't a blanket plane. Any advice on that would be helpful.
From the layout guidelines, this next line doesn't seem to make sense to me. Are there some words missing? or should it say "or through the large analog" ...
Do not connect COUT and CIN grounds underneath the device and through the large analog ground plane
which is connected to EP.
regards
Kari
