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TPS767D3: unexpected reset

Christophe Ahrens
Prodigy 10 points
Part Number: TPS767D3

Tool/software:

We need support with the TPS767D301PWP LDO regulator implemented in one of our board.

A customer is complaining about unexpected reset generated by the LDO.

The LDO us used with a 5V input voltage to generate 1.9V and 3.3V output voltages.

We made tests with variations of input voltage, and we notice that the reset is generated as soon as the input voltage drop under 4.65V.

According to the datasheet the minimum input voltage is VOUT + Dropout = 3.3V + 0.575 = 3.875V

Can you help us to understand why we have this reset generated at 4.65V ?

The output voltages are still working correctly when the reset is generated.

 

Below the implementation of the LDO in our board :

  • 0
    TI__Genius 12910 points

    Hi Christophe,

    A 4.65V input should provide enough headroom to provide both the 3.3V and 1.9V outputs. My only concern with the schematic as shown is the output capacitor ESR. TPS767D3 requires an output capacitor ESR of 60mΩ to 1.5Ω for stability. While the ferrite beads will add some series resistance to the 1µF ceramic capacitors, the effective ESR at the output could still be low enough to cause a possible stability issue.

    Does either the 3.3V or 1.9V output show any signs of unusual output transients (even very short duration) or ringing? A fast transient drop on either output could potentially fall below the reset threshold, causing this behavior.

    Best Regards,

    Alex Davis