TPS543B20: Operation Mode Error (does not match datasheet)

Hi Michael,

The device will sync to clock once the external clock is applied

Best regards,
Britton

Please understand that the sync pin is actually operating as an output. In this case it is connected (via a zero ohm link) to an FPGA port pin. Due to voltage compatibility of the FPGA pin bank I need to disconnect it from my FPGA, even if I connect it to a 3V3 bank (which I don't currently have) it would not meet the power sequence requirements presenting a signal prior to the bank voltage being applied. The output waveform is around 3V3 level. It is not possible that it is an input and also an output in my mind. Is it possible that the mode is not detected correctly or that the datasheet is in error in saying I can use the sync pin as an input with the mode value set to 78.7kOhms? 

Hi Michael,

If an external clock is applied to SYNC at startup then the device will sync to the external clock. If there is no external clock applied to sync then the frequency will be set by the RT resistor and the SYNC pin will output the device frequency. What you are seeing is not a mistake

Best regards,
Britton

Thank you this is helpful information. In the case of my design the PSU is used for the core voltage to an FPGA and I cannot apply the clock signal until the FPGA has run through the power up sequence and configuration also it is not configured until other parts in the system are booted up which takes some number of seconds. Is there a way I can keep the part waiting for an input clock to sync while running at the value given by the RT resistor then sync the part to a exact clock much later? Synchronizing the clock helps to keep noise out of a receive band we are using and is important for the design but at this stage of the development I don't have the option to add an additional accurate clock source to synchronize the part to.

The frequency will not update on-the-fly. It will attempt to match the external clock frequency on-the-fly but will result in instability. For your case, you will need to do the following: disable TPS543B20 by pulling EN low. Apply power to your FPGA and to TPS543B20. Once the start up sequence has completed, apply the external clock signal. Finally, enable TPS543B20 by pulling EN high

This is not a possible solution since the FPGA is running off the TPS543B20 on the core voltage (0.9V) This is the first PSU in the sequence for the FPGA. It has to be on first and syncronised later. By syncronsing from the FPGA I can adjust the frienciese to resolve any unwanted mixing getting into my receive band. If I choose a single fixed frequency source for PSU it would require a significant change to the hardware on a design that is basically complete and would not allow adjustment. If I apply a pulldown resisor or something can I force it to not output the clock? I could adjust slowly to the target frequency after fully ready. Thank you