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UCD3138A: EADC conversion time and maximum frequency? continuous sample

Javier G
Prodigy 20 points
Part Number: UCD3138A
Other Parts Discussed in Thread: UCD3138, UCD3138R

Tool/software:

Hi,

I am working on implementing peak current control with the UCD3138. My control approach requires very fast sampling and update during the on-time. Specifically:

  • Within the first ~300 ns of the switching cycle, I would like to sample the primary current as often as possible.

  • The idea is to sample at t = 0 ns, process the filter (2P2Z or similar), generate the compensation ramp, and if the ramp crosses the measured current, then immediately fault/turn off the DPWM.

  • If not, then I would like to re-sample again after the minimum step time (I saw 62.5 ns mentioned in the datasheet). At each sample/update, I would recalculate the filter output, adjust the ramp reference, and continue until a crossing with the primary current occurs.

My questions are:

  1. Is the 62.5 ns step size realistic for continuous ADC sampling and digital filter update?

  2. Does the 62.5 ns include the time required for the filter calculation, or only the raw ADC sampling interval?

  3. What is the fastest achievable sampling rate on the UCD3138 for this type of control loop?

  4. I have seen that the ADC can be triggered by several sources (such as DPWM frame start, output pins, etc.), but I don’t see any way to configure it to sample repeatedly at the maximum possible rate. How should I set up the sampling triggers or clocking so that I get the fastest possible continuous sampling? Where in the documentation can I find the exact configuration registers or limits?

Thank you very much for your help,

  • 0
    TI__Genius 9550 points

    Hello Javier,

    Below are my response to your questions

    1. Is the 62.5 ns step size realistic for continuous ADC sampling and digital filter update?

    I assume you are referring to the Front End error ADC (eADC), not the general purpose 12-bit ADC. Yes, the Front End eADC has a maximum sampling rate of 16MHz, or 62.5ns. However, this only refers to the sampling rate of the Front End itself, and does not include any modules after it. 

    2. Does the 62.5 ns include the time required for the filter calculation, or only the raw ADC sampling interval?

    The minimum time it takes between a sample trigger and a DPWM moving edge based off the Front End eADC measurement is 450ns in the UCD3138. We also have the Event Update Window (EUW), which is the time it takes for the DPWM moving edge to update its position after reading the PID output. This is 72ns in the UCD3138. Fixed edges can still occur in the EUW (Ex. if Event 1 is fixed, you can have it in the EUW), but a moving edge cannot be in the EUW). 

    See the "Event Update Select" section on page 55 of the TRM. 

    Below is a comparison of the Event Update Window and Sample Trigger to CLA Processing Window. The Sample Trigger to CLA Processing Window is the time it takes for the Front End sample to generate a PID output while the EUW is the time it takes for the PID output to update the DPWM moving edge position. The upcoming UCD3138R will have a much faster processing time. Please contact your local FAE for more information on the UCD3138R.

    3. What is the fastest achievable sampling rate on the UCD3138 for this type of control loop?

    See above.

    4. I have seen that the ADC can be triggered by several sources (such as DPWM frame start, output pins, etc.), but I don’t see any way to configure it to sample repeatedly at the maximum possible rate. How should I set up the sampling triggers or clocking so that I get the fastest possible continuous sampling? Where in the documentation can I find the exact configuration registers or limits?

    See the "EADC Timing" section on page 113 of the TRM. 

    Our UCD3138PSFBEVM-027 uses Peak Current Mode Control (PCMC) for the PSFB topology. You can view the UCD3138FW-PSFB for example code. 

    Regards,

    Jonathan Wong