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LM5012: Load Step Response

Arman Hojjatoleslami
Prodigy 10 points
Part Number: LM5012


Tool/software:

I am evaluating the LM5012 in a buck converter design and comparing my results with the datasheet application curves.

Figure 9-5 in the datasheet shows a much faster transient response than I am observing. Can you confirm what output capacitance was used in those measurements?

With a 0-2 A load step (2 µs edge rate), my circuit shows:

- Overshoot to about 3.7 V on a 3.3 V rail when the load returns to 0 A.

- Settling time of roughly 700 µs.

This looks quite a bit slower than the datasheet plot, so I wanted to check if I might be missing something in my setup or compensation.

Thanks!

  • 0
    TI__Genius 12140 points

    Hello Arman,

    I see the datasheet capture goes from 1A to 2.5 were your's starts from zero is most likely a contributing factor to the datasheet looking better. I am unable to find the output capacitance used listed in the DS. 

    Regards, 

    Oscar Ambriz 

  • 0 in reply to Oscar Ambriz
    Prodigy 10 points

    Hi Oscar,

    You are right about that.

    On another note, I'm also finding that my steady state voltage is higher than what is expected from the feedback loop both in the Webench simulation and in my scope shot.

    With a 200k and 113k configuration I expect a voltage of 3.32V but in simulation I get 3.5V and in application I get 3.4V.

    Can a TI member provide the feedback pin input current specs and the spice files for the LM5012 to better simulate my setup?

  • 0 in reply to Arman Hojjatoleslami
    TI__Genius 12140 points

    Hello Arman, 

    Currently looking into this will respond back shortly 

  • 0 in reply to Oscar Ambriz
    TI__Genius 12140 points

    Hello Arman, 

    Take note that the reference voltage of the device does have a max and min, this could have an influence on your output voltage. 

    Additionally the accuracy of the resistors used will have an influence. For example 5% resistors can lead to greater variation in output voltage compared to 1% resistors. Unfortunately, i have consulted the team and there does not appear to be a simulation model available at this time. 

    Regards, 

    Oscar Ambriz 

  • 0 in reply to Oscar Ambriz
    Prodigy 10 points

    Hi Oscar,

    Yes, I've looked into that as well. 
    Considering the absolute worst-case tolerance of my 1% resistors and the Vref variation, my output voltage makes sense.

    I just wanted to confirm that I wasn’t overlooking any other factors, specifically whether the input bias current of the feedback pin could have been influencing the voltage divider.

    Thanks,

    Arman

  • 0 in reply to Arman Hojjatoleslami
    TI__Genius 12140 points

    Hello Arman,

    Your number look good, that is typically what i would expect. I don't believe there is anything being over looked in this case. 

    Regards, 

    Oscar Ambriz