Hi team,
The ACTIVE state is defined as ‘the state where all valid buck converters and LDOs are operating’. Therefore, we consider that a RESET request becomes effective only after the power-on sequence is complete and the device enters the "ACTIVE state".
To ensure the configuration does not transition to the "STBY state", I consider the RESET pin to be active only in the "ACTIVE state".
The MODE/RESET setting is used as the RESET pin and is pulled up in Buck 2.
Is our understanding of the active and inactive periods for the RESET request in the timing chart below correct?
I consider the yellow portion to be the active period.
Is it acceptable for the RESET pin to temporarily fluctuate from L→H→L during sequencing down?

Best Regards,
Ryu.
