• State Resolved
  • Replies 3 replies
  • Answers 1 answer
  • Subscribers 63 subscribers
  • Views 46 views
  • Users 0 members are here
Support feedback
Options
Options
Related

PARALLEL-LDO-CALC: LDOs Parallel using TPS7A85 - design review

Antonio Girardi
Prodigy 40 points
Part Number: PARALLEL-LDO-CALC


Hi, i'd like to ask for help in verifying a circuit i've designed (FPGA's core power supply). The constraints can be seen in the Excel spreadsheet (see images).
1) I used 1% tolerances for both the ballast resistors and the voltage regulation resistors. Is this ok, or is it worth looking for 0.1% components? (actually i did some tests with the spreadsheet and it doesn't seem to make much difference, but I'd like your opinion).
2) The optimal ballast resistor recommended by the Excel spreadsheet seems rather large and will produce a voltage drop. Will it be necessary to compensate for the LDO voltage, right? For example by adjusting output to 1.05V?
3) Is the physical layout ok? For the LDO output section, i've decided to avoid using traces, that could vary in resistance with temperature, and to use only the ballast resistors for the connection. what do you think?

Thank you, greetings

 

Schematic.jpg

calc.jpg

PCB.jpg

  • +1
    TI__Expert 6130 points

    Hi Antionio,

    Thank you for asking us!

    1) 0.1% tolerance isn't really necessary unless you need to squeeze every last bit of accuracy out of the device. You get diminishing returns once you go below the part's rated accuracy. Resistors from the same reel are typically pretty well matched so the relative accuracy between parallel LDOs is likely going to be significantly better than accuracy compared to Vout nominal.

    2) The ballast resistor will add roughly ~9.25mV/A (0.037/4 if they are all sharing perfectly current equally) effective load regulation to parallel system. You may increase the nominal VOUT the counteract this for typical load (~1.01V if expecting 1A, etc), but it will worsen accuracy at no load conditions. 

    3) The layout looks good to me. Polygons are large enough to avoid many parasitcs and ground loops look good.

    Best,

    Gregory Thompson

  • 0 in reply to Gregory Thompson
    Prodigy 40 points

    Hi Gregory,

    thanks for the reply and for validating the design.

    Such a large voltage drop (3.5V to 1V) with current up to nearly 2 amps isn't always easy to handle using only LDOs.

    Best,

    Antonio

  • 0 in reply to Antonio Girardi
    TI__Expert 6130 points

    Hi Antonio,

    Power dissipation is always a problem with LDOs.

    One little trick you can use to move power dissipation out of the device is have a resistor right before the device. This will significantly worsen dropout (dropout is essentially the lower limit of the pass element's RDS, adding series resistance increases the system's minimum VIN to VOUT resistance), but given the device and voltages there is enough room to work with there. As long as the VIN is high enough, this doesn't really effect the devices performance. Roughly 10Ω or lower should be than sufficient even if all the current was sourced from a single device, you want a bit of extra headroom so the device isn't barely above dropout.

    RθJA is benchmarked with a JEDEC high-k standard board (74.2mm x 74.2mm, two 2oz trace layers, and two 1oz buried planes, JESD51-7), so any improvements over that will improve your board's RθJA and the parts thermals.

    I spoke with the engineer who wrote the calculator and thought I'd give you some further comments.

    You can get some noise improvements by kelvin sensing for the feedback. Connect the top feedback resistor with the high side of the ballast resistor as close as possible. There are also some benefits to impedance matching the path between the ballast resistor power plane point of contacts and and load point-of-contact. The closer the noise is to the ideal sqrt(n) factor, the more evenly your current is shared and the more even your power dissipation will be.

    Best,

    Gregory Thompson