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TPS54531: Question about reducing number of bypass capacitors

ArTzy
Mastermind 18580 points
Part Number: TPS54531


Dear TI Support,

I am currently designing a circuit using the TPS54531DDAR.
In the datasheet's "9.2 Typical Application" section, multiple bypass capacitors (e.g., C1, C2, C3) are connected in parallel at the VIN input.

To reduce BOM cost, I would like to reduce the number of bypass capacitors, while keeping the total capacitance unchanged (for example, changing from 3 × 4.7 µF to 1 × 10 µF).

Could you please advise on the impact of reducing the number of capacitors in this way, specifically regarding device performance, stability, or noise characteristics?

Also, if such a change is acceptable, are there any points we should pay attention to in terms of component selection, ESR, layout, etc.?

Thank you very much for your support.

Best regards,
Ren

  • 0
    TI__Genius 11755 points

    The guidance for this specific part states that 10uF is recommended as long as it meets all requirements, that is voltage and current ripple. I would have the solder pads available on your design but leave them as DNP. Try using a 1 x 10uF and see if the design is robust. The one thing that I know will be affected is equivalent ESR. You are effectively reducing 3 parallel current paths to 1, so the resistance across the cap will be larger than with 3 x 47uF.

    ESR comes into play in this equation. So long as you aren't above the Absolute maximum or below the UVLO threshold for PVIN, then you should be okay. 
    I recommend that you keep the 10nF capacitor close to the input for filtering high frequencies.

    Thanks,
    Caleb