Hello Experts,
I am a hardware design engineer using the TPS16530RGER in a power delivery function in a product line. The design is in the late development stage. I have a second revision hardware PCB assembly prototype that is experiencing an unusual anomaly. See the schematic below for our specific circuit implementation. Basically, transient analysis of all pins/nodes on the TPS1653 are behaving as expected except one crucial parameter in one very important use case. The design uses the TPS1653 to deliver ~ +48 V to a RJ-45 connector.

When I current limit the supply voltage to VIN (Pins 1, 2) using a voltage supply and gradually increase the current manually over 5-10 seconds, the output VOUT (Pins 17, 18) works completely as expected. The hardware current limit ILIM set using R_ILIM limits at the expected current (~3 A in my configuration). However, when I do not current limit VIN gradually, effectively just turning on the power supply for a quicker VIN rise time (~100 ms to rise to +48 V on VIN), VOUT ramps linearly as expected per the DVDT external capacitor (pin 9), rises to ~23 V then suddenly decreases exponentially to ~6 V over ~100 ms, then very gradually decreases from ~ +6 V to ~ +3 V over ~1.3 s. Then the TPS1653 faults and the output shuts down completely.
In my test setup, I am outputting to an RJ-45 connector to a high-power load resistor setup. Other than the 10 uF bulk capacitor shown in the schematic diagram (on the PCB), I am not using any other external capacitance on the test loads. Most importantly, this behavior only occurs with a load resistor configuration such that the output current is greater than ~1.65 A. With an external load resulting in 1.65 A or less at +48 V, VOUT ramps normally, reaches 48 V, and everything is fine. Greater than ~1.65 A, and it will not rise all the way to 48 V and behaves as described above when VIN is “switched on” without voltage supply current limiting.
Again, during this rise and fall, all other pins on the chip behave as expected when viewed on an oscilloscope. I use the TPS1653 on 12 channels, with one TPS1653 per channel and one RJ-45 connector per channel as well. I’ve combed the TPS1653 datasheet layout guidelines, and I am following it as closely and reasonably as possible. The 4-layer stack is:
Top - Signal
Internal 1 - Ground plane
Internal 2 - Voltage planes
Bottom – Mixed: Signal (sparsely), voltage planes
Have you ever encountered anything like this? Any idea what could be causing this behavior?
Regards,
Aaron