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TPS7A02: High ground current

Bardia Bandali
Prodigy 20 points

Part Number: TPS7A02

Hi,

We have used a TPS7A0233 in one our products that is supplied by a Li-ion battery. The whole board is supplied by this LDO which is always ON, and there is no other parts on Vbat line. The overall current consumption in shutdown mode at Vbat<3.6v is about 200nA. However, at higher Vbat the board shutdown current increases up to 140uA at Vbat=4.2v. This is has been confimed by testing on several boards, and also by replacing the LDO with a simple diode where the shutdown current becomes less than 500nA at Vbat=4.2v (board Vcc becomes ~4.0v).  

Apparently, this is the ground current of the LDO, but considering the datasheet, we did not expect such high current when Iout=200nA. 

Could you please inform us if there is remedy for this? Or, introduce us a replacement part without such high ground current at higher input voltage?

Thanks in advance

 

  • 0
    TI__Genius 15834 points

    Hey Bardia.

    In order to help diagnose this issue can you please provide the following information/ answer the following questions.

    • Schematic
    • Vout
    • Ambient temperature
    • How are you measuring ground current?

    Thanks,

    Vahnroy

  • 0 in reply to Vahnroy Hosear
    Prodigy 20 points

    Hi Vahnroy,

    Thanks for the reply. Following is the schematic. 

    Vout is 3.3v as the part is TPS7A0233 and measurement is done in room temperature (23c).

    I simpley measure the current through JP2 and JP3. Obviously, Vout stays at 3.3v when Vbat=4.2v but the input current is ~140uA while the output current is ~170nA.

    I mentioned "apparently". Perhaps it would be better to call it quiscent current?  

    Please note when Vbat=3.6v the input current is about ~200nA.

    Regards,

  • 0 in reply to Bardia Bandali
    TI__Genius 15834 points

    Hey Bardia,

    Are you not utilizing an output capacitor?

    Thanks,

    Vahnroy

  • 0 in reply to Vahnroy Hosear
    Prodigy 20 points

    Hi Vahnroy,

    We do have output capacitors for LDO. The C4 capacitor is almost attached to U7 and C6 is 3mm away from it, see below pic.

    FYI, the whole PCB size is 7.8mm x 8.8mm.

    Regards,

  • 0 in reply to Bardia Bandali
    TI__Genius 15834 points

    Hey Bardia,

    Thanks for sharing the schematic and layout. At this point it’s difficult to correlate the behavior you’re seeing because the schematic does not match the actual PCB implementation. Since ground-return behavior and LDO quiescent current paths are very layout-dependent, any mismatch between schematic and layout makes it hard to determine where the ground current is flowing

    Would you be able to provide a more accurate schematic?

    Thanks,

    Vahnroy

  • 0 in reply to Vahnroy Hosear
    Prodigy 20 points

    Hi Vahnro,

    I made and tested a separate board.

    I can confirm that the issue is not related to LDO itself and most probably as you mentioned it is due to power/groud routing in PCB. We have decided to redesign the PCB. Do you have any recommendation?

    Regards,

  • +1 in reply to Bardia Bandali
    TI__Genius 15834 points

    Thanks for the update, and I’m glad to hear that the standalone board confirmed the LDO itself isn’t the source of the issue.

    For the redesign, here are a few recommendations that typically improve LDO stability and help avoid unexpected ground-return paths:

    1. Star-Ground or Clean Ground Return
      • Make sure the LDO ground pin has a direct, low impedance return path to the main system ground.
      • Avoid sharing this return path with high-current or noisy digital grounds.
    2. Short, Wide Traces for Input and Output Paths
      • Keep the input capacitor, output capacitor, and LDO pins as close together as possible.
      • Use wide traces or planes for VIN, VOUT, and GND to reduce parasitic inductance.
    3. Local Decoupling
      • Place the LDO input capacitor right next to the input pin and the ground pin.
      • Same for the output capacitor. close placement significantly affects stability.
    4. Ground Plane Under the LDO
      • Use a solid ground plane underneath the device if possible and connect the thermal/ground pad (if the package has one) with plenty of vias.
    5. Avoid Return-Path Interference
      • Make sure high-current switching components (e.g., DC-DC converters, digital logic, motors, LEDs) don’t share ground paths with the LDO’s ground return.
    6. Minimize Loop Area
      • The LDO’s input cap, output cap, and ground connection should form the smallest loop possible.

    Thanks,

    Vahnroy