Disappearing R_DIS and VOK

Both R_DIS and VOK are bits that will toggle on and off. If there is not enough relaxation time and the gas gauge is not able to have a successful OCV reading. YOu may see VOK is off and R_DIS is on all the time. Below is the set/clear conditions for both bits.

-- VOK set and clear condition --
VOK set condition is that last OCV reading is qualified for
Qmax update.
All of the following needs to be satisfied for VOK to be
set:
1)   dV/dt<4uV/sec
2)   voltage outside of disqualification window
3)   temperature below 40C and above 10C

VOK set (if all above conditions for last OCV reading are
satisfied) when:
-    discharge starts
-    charge starts
-    IT enable command is sent.

Note that VOK is NOT set at OCV measurement itself, because
OCV measurements will continue until discharge or charge
will start.

VOK clears when:

-    Qmax update took place
-    timer for CC-offset error accumulation has reached
estimated 1% error of presently passed charge.
  Offset error accumulation assumes 10uV offset, so with
  10mOh sense resistor it assumes estimated 1mA error
  current.
  - on Full Reset (because OCV measurement after reset is
  considered not accurate enough).


-- R_DIS set and clear condition --

R_DIS may be set because of one of the following reason

a)      Charge accumulation error > 2% of Design Capacity, or

b)     During Discharging, we have a bad resistance update

• Computed resistance is negative (R < 0), or
• if the new resistance scale factor is too large or too small

Charge accumulation error can exceed the 2% threshold if DOD₀ fails to update during the Relax phase, or the pack is not given sufficient rest - bad/no OCV reading.

Once OCV reading is taken in relax mode, R_DIS is cleared.

I understand the will turn off or on. The problem is both R_DIS and VOK are off.  How is that possible? QEN is on.

I understand they will turn off or on. The problem is both R_DIS and VOK are off.  How is that possible? QEN is on.

After 2 CHG/DSG cycles a pack was allowed to rest for 24h. It was then tested and was fine (test includes brief chg and dsg tests of less than 3sec ea and a SC test). The pack then rested for another five days and when retested R_DIS and VOK were set. (See inserted screen capture).

Many of our production packs are tested this way (without the CHG/DSG cycles) and we don't see R_DIS becoming set.

The pack was relaxing for 5 days, so according to JH's response above ("Once OCV reading is taken in relax mode, R_DIS is cleared.") R_DIS should have not been set.

Questions:

1. The pack was relaxing for 5 days, so according to response above ("Once OCV reading is taken in relax mode, R_DIS is cleared.") R_DIS should have not been set. Is that correct?

2. That R_DIS became set does it indicate there are issues with this pack, or it is a matter of no concern and the pack can be considered good?

3. Is there an easy way to validate/test for this?

4. Are these flags not exclusive of each other, or what would set both simultaneously?

Thank you!

Hi Alexander,

Having the Rdis bit set during relaxation is not an anomaly and is not an indication of a problem. It simply means that resistance table update was disabled, this is temporary and once you have current flowing during discharge, as long as it is greater than c/10 you will have resistance updates. 

thanks

Onyx