We’re seeing a problem with GPIO outputs on the UCD90160 power manager. We initially noticed the problem with GPIO2, which we’re using as the System-Reset to drive a low-going pulse to another device which uses this pulse to begin its power-up. The input on the downstream device is 5V, so we’re using an SN74LVC1G07 open drain buffer to translate from the 3.3V power manager to 5V logic, with a pullup resistor on each side of the buffer.
The UCD90160 datasheet states that the GPIOs (except the FPWM/GPIOs, which GPIO2 is not) are high-impedance during reset, and the UCD90160 stays in reset until Vdd (3.3V) reaches 2.4V. While the 3.3V rail is ramping up, we expect to see the voltage on GPIO2 follow the 3.3V rail since it’s pulled up, but we actually see a short glitch on GPIO2 where the pin appears to be driven low. The glitch begins when Vdd reaches ~0.7V and continues until Vdd reaches ~1.0V, after which GPIO2 follows the 3.3V rail again. This low pulse goes through the 1G07 and to the downstream device, which begins its power-up sooner than we want.
We’ve found similar glitches on other GPIO pins on this board and other boards. The downstream functions on the other pins are not as sensitive to the glitch as GPIO2, but we are still concerned about it. The glitch is not affected by the programming of the GPIO pins, and it occurs before the UCD90160 comes out of power-on reset. We would like to understand the root cause before choosing a workaround.
