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LM5148: LM5148 OCP issue

Wayne Jhang
Prodigy 10 points

Part Number: LM5148
Other Parts Discussed in Thread: TEST2,

Hello Specialist,

[Issue]

In my testing, the system enters OCP earlier than expected.

[Test condition]

Vin=24V, 30V & 36V (VDD_SRC)

Vout=12V (Measure by VOM)

Switching frequency=678kHz 

Rsense=5m ohm

Choke=4.7uH ( DCR=7m ohm, Irms=13.5A, Isat=26A)

Test1:

Vin = 24V, Vout = 12V
- Load current from 1A to 7.5A: output is 12V
- At 8A load: output voltage drops to ~7V

Test2:

Vin = 30V, Vout = 12V
- Load current from 1A to 6A: output is 12V
- At 7A load: output voltage drops to ~10V

Test3:

Vin = 36V, Vout = 12V
- Load current from 1A to 6A: output is 12V
- At 7A load: output voltage drops to ~10V

Test4:

Modify C158 to 820pF, the results remain the same as in the previous tests.

Test5:

Modify Fsw 350kHz , the results remain the same as in the previous tests.

Any recommend what to check or improve to avoid early OCP triggering?

 

 

 

  • 0
    TI__Mastermind 19820 points

    Thanks for your question

    we will look into it and get back to you

  • +1 in reply to Naresh Adepu
    TI__Mastermind 19820 points

    Hello Wayne

    Thank you for the detailed test results, schematics, and images on the LM5148 OCP issue in TEST2. The steady-state current staying below expected peak limits and consistent results up to 250kHz (with no early OCP at low frequency) help narrow this down significantly.


    Key Observations:
    • VCL > VCC violates LM5148 operation (VCC regulates ~5V; VCL must stay ≤ VCC to avoid undefined behavior).
    • Schematics show VCL connected post-filter to COL (likely CS amp output); excessive ripple or noise on ISNS+/VOUT could clamp/boost VCL erroneously.
    • Peak current limit trips at VCS-TH = 60mV (typ) across ISNS+ to VOUT; your loads (up to 7A) align if Rsense/DCR scales correctly, but early entry suggests sensitivity or offset.


    Recommended Checks:
    • Measure DC voltages: Confirm VCL ≤ VCC (5V) steady-state; scope VCL ripple (<100mV ideal).
    • CS path validation: Kelvin-check ISNS+ to VOUT differential (expect <60mV peak); verify Rsense (or DCR+RC) matches expected Ipk.
    • Noise/loop stability: Scope SW, ISNS+ for ringing >60mV; check EXTCOMP (internal comp if floating) for oscillation.
    • Temp effects: RSEN temp coeff or RSETA heating could shift limit; retest at 85°C if not done.


    Next Steps:
    If VCL ≤ VCC holds and CS measures ~60mV at 7A (no excess), recommend:
    Update Rsense slightly higher to desensitize.
    Add CS filter cap (10-47pF) if ripple evident.
    Re-test full matrix (24-30V in, 100kHz-500kHz).

    Hope this helps

    Thanks and regards

    Naresh

  • 0 in reply to Naresh Adepu
    Prodigy 10 points

    Thank you for your response. I will try it.