• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 63 subscribers
  • Views 260 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

overshoot question

Gaston_Melo_Arg
Mastermind 7675 points

Hi to all,

I read the spraab3 pdf (http://www.ti.com/general/docs/litabsmultiplefilelist.tsp?literatureNumber=spraab3) and using matlab , for a computation delay of 0.5Ts (pag 9 pdf , were Ts= sampling time of 4e-6 sec)  i see a 38%  overshoot for the step response. I used the model of the plant and the controller that appears in the pdf (pag 9, discrete models) to do the step response.

I want to know if this is correct and i have a few questions about it:

1) This overshoot would damage the electronics connected to this dc-dc converter?(I guess it would... )

2)  ways to reduce this overshoot, trying to maintain the controller specifications?

Thanks for your answer, i´m trying to build my own dc-dc converter.

Regards.

Gastón

  • 0
    TI__Guru**** 191445 points

    It is typical to get undershoot on load step and overshoot on load dump.  the best way to reduce that is to increase the output capacitance and reduce ESR.  You have to determine what your load circuit can tolerate and design accordingly.

  • 0 in reply to JohnTucker
    Mastermind 7675 points

    Thanks Tucker for the quick reply. I was trying to keep the settling time (less than 76us). Because if I go for less overshoot (industial tipically less 10%) i need a phase margin more than 60 degrees (settling time >>76us).

    If i use a super cap as output capacitor, do i need to take some considerations? (2.5V super cap)

    thanks for your quick answer

    regards

    Gastón

  • 0 in reply to Gaston_Melo_Arg
    TI__Guru**** 191445 points

    I do not have any specific knowledge of that application.  I was only making a general comment that higher capacitance and lower ESR will result in lower voltage deviation to transient load step.  For the integrated FET converters that I work with , Low ESR SP types usually work well.  Super caps usually have  very high capacitance and relatively large ESR compared to special polymer types that I would normally recommend.  Perhaps the autor of that application note you reference will contribute to the thread.