Hello.
I am a power supply circuit designer . These days, I'm designing the buck converter using UC1843 (military application)
So the rough circuit concept and specification are the below
1. Input voltage range: DC 40 ~ 108V, nominal 80V
2. Output voltage and current: DC 28V@19A , approximately 540W
3. Non-isolated, synchronous rectification ( Driving high side FET by using pulse transformer )
While pre-desinging, Two main issues are coming up.
First, according to PSIM simulation, there is sub-oscillation above 50% of duty-cycle. Recommended slope compensation techniques cannot be used because of no using current mode. At this time, I'm not sensing any switching current or inductor current ( Instead, for OCP, I just sense the output current, and push it into the current sense pin of IC)
It is hard to understand sub-oscillation in buck-converter. In my knowledge, CCM mode buck converter dosen't have any RHPZ in its control-to-ouput transfer function.
Second problem is driving high/low side FET by pulse transformer.
As you know, there are many precautions on designing pulse transformer, particularly when single output pulse of IC is used to drive high and low side FET.
For blocking transformer saturation, additional cap in series of primary winding.
And for damping out the resonance by C and Lm, additional resistor in series of that.
and blah, blah
In my opnion, these techniques result in distortion the soure driving pulse.
TI some application note (slup169) mentioned "DC restore circuit in transformer coupled gate drive"
I'm not sure of that. particularly above 50% duty-cyle.
Is there anyone who had been these problem in the past? or have any idea on these?
