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[TPS65911] PWRON_LP_RST behavior

Antony Lin
Genius 13480 points

In the document "TPS659110_Digital_General_Reset.pdf,"  there's some description regarding PWRON_LP behavior under different DEVON / AUTODEVON setting.

Can you help to provide information regarding the case of below condition after long PWRON press is triggered?  What will happen and why?

  • PWRON_LP_OFF=0
  • PWRON_LP_RST=1
  • DEVON=1
  • AUTODEVON=1

Thanks!

Antony

 

  • 0
    TI__Intellectual 2090 points

    In this case after a Long key press the device will restart. Because The long key press is configured to do a general reset so DEVON register bit will be reset to DEVON=1 as defined in the EEPROM.

     

  • 0 in reply to Fabian Stel
    TI__Genius 13480 points

     Hi Fabian,

     

    Actually below table is provided by Gandhar prevuisly with AUTO_DEVON=1 in EEPROM,    The question I asked for is case 3 withi nthis table.  It seems his result is different from your description?  Can you try it on your board? 

     

    Besdies, you mention  "The long key press is configured to do a general reset" in this case.  But based on the definition of PWON_LP_RST, it's defined as "When 1, allows digital core reset when the device is OFF"  But for case 3, I can't see who put the device in off since PWON_LP_OFF is '0'??

    PWON_LP_RST  PWON_LP_OFF  RESULT after Long Press (LP) PWRON 
    1 1 PMIC switch OFF, stays OFF after LP released 
    0 1 Device OFF after LP, Device restart when LP released 
    1 0 Device switch off, stays OFF after LP released 
    0 0 No effect

     

    Thanks,

    Antony

     

  • 0 in reply to Antony Lin
    TI__Intellectual 2090 points

    I made this table for a better understanding. Please use this as the reference

    0576.START_and_RESTART_Condition_Linked_to_EEPROM_SETTINGS_REV1P0.xls

  • 0 in reply to Fabian Stel
    TI__Genius 13480 points

    Hi Fabian,

    Thanks a lot for the excel file composed.  I quote the table from it as below.  My questions are,

    • Q1: When PWRON is pressed longer than 4sec, PWRON_LP_IT will be generated.  After this, what's the different impact to PMIC if PWRON_LP_IT is cleared or not within 1 sec (=tdPWRONLPTO)?
    • Q2: In Case2, PMIC should be turned off after 4sec+1sec since PWON_LP_OFF is '1'.  Since PWON_LP_RST=0, DEV_ON should stay as the original value before PMIC is off.  Considering DEV_ON is '1' before PMIC is off, PMIC should start automatically after PWRON is released to high level. correct?
    • Q3.: I'm not sure if we need to define PWON_LP_RST clearer.  In datasheet, it's defined as "allows digital core reset when the device is OFF." 
    • This means PWON_LP_RST is not meaningful if PMIC does not enter OFF mode, right?
    • Conidering PWON_LP_OFF=0 in case3, PWRON_LP won't turn off PMIC, correct?
    • If the answer is true for above 2 questions, I think "PWON_LP_RST=1" won't reset digital core considering PWON_LP_OFF=0 in case3, right? 
    PWRON_LP (pin) PWON_LP_OFF PWON_LP_RST PWRON_IT (if not masked) PWRON_LP_IT (if not masked) Device state
    1    (case1) 0 0 1 1 no impact => stay active
    1    (case2) 1 0 1 1 switch off (turn off reset) 1s after IT gen it cleared =>
    1    (case3) x 1 1 1 switch off (General reset) 1s after IT generated accept if it cleared =>

    Antony

  • 0 in reply to Antony Lin
    TI__Intellectual 2090 points

    Q1=>  if the IT is cleared the PMIC will not switch OFF. Else the PMIC will switch OFF.
    Q2=> Correct
    Q3=> in this case 3, the x means that PWON_LP_OFF state is don't care. So, atfer a Long key press action the device will switch off (General reset) 1s after IT generated accept if it cleared