TPS54613, TPS54910 power good output to SS/ENA input oscillation

This looks like another issue we are working.  Is second output 3.3 V?  Is there any pre-bias on the TPS54910 output?  Is (or was) the other output TPS54616 instead of TPS54910? 

John"

Possibly: can you tell me if this is from my company?

If not, tell me if this is from Boston?

My question was forwarded to you by George Biner: so you can track me from there

or respond  here. Prefer: You can call me at  818 523 8735 Thursday Ca  time before 8:45 am or after 1pm CA time. Certain things cannot be posted in public.

John:

Yes, the 1.5V  controller is TPS54613. Its PGOOD is connected directly to the SS/ENA of the TPS54616

There are several hundred moduels produced; all work in room temp.

In some moduels at -25 deg C  , the  common node PGOOD from 1.5V to SS/ENA pin of  TPS54616 oscillates with 1.5V output steady. Of course the 3.3V output goes through ups & downs. AT fairly low frequencies.

Question is: who causes it? IS it possible the the open drain fed by a comparator only oscillates  because of some peculiarities in the 54616 SS current course that shows up only at low temps?

We have postulated that this is a possible scenario & have decided to add an external pull up with 68.1k

Can you propose any other viable explanation? Why wont it happen randomly if there some inherent root cause to break out in limti cylce in the comparator?

John:

Allow me to say some words about the layout instruction and other notes in the applications section of TPS54910(for example)

#1 The suggested routing of the AGND path is contestable.  This suggestion is repeated in almost all TPS family chips, or wherever AGND/PGND exist. Here is my take on this: in my routing, I would suggest making the AGND nodes interconnected in such a manner that reduces parasitic elements to the most. For example, I would suggest that it is far more defendable to have an "island" of copper devoted in an inner layer so that AGND nodes interconnect without any  inductance. Now, extend this to a case where we have 9 such sections in a PCB: Would you have 9 islands spread all over? That would impede seriously placing other chips of high pin/ball count(such as BGA etc).  Why not make 1 AGND plane where AGND nodes  are localized . We also have multiple PGND planes. The AGND planes make "single point" connection to the PGND planes only at  the power entry point. This elaborate method surely provides for least  inductive paths for all AGND & PGND nodes.

If you show a a trace to interconnect AGND pins for ONE chip, I notice for many people this means THAT IS THE ONLY WAY  route & ANY problem is said to arise because  "we did not follow vendor recommendations"

Although, problems are no at all related to this "low impedance quiet" GND approach I described. Of course, understand that our PCB is 24 -layer structure loaded with various planes: such as AGND, DGND, SGND, PGND.

#2  It is said in the app note that SS capacitor is required in order to "control inrush current".

   I would like to point out that in a buck converter, there is no such thing as "inrush” current.. All drain currents are limited by the non-saturating inductor before the filter capacitor banks. So  hi-side current is always (V/L)*dt.  Agreed, without an SS capacitor, the RATE if rise of dI will be faster than with the cap. But this is not called "inrush current".

Would appreciate your thoughtful analysis of the above.

There are probably multiple ways to route grounds.  I usually like to have a separate analog gound area for each sub circuit or converter and tie it locally at a single point to reduce circulating currents from the power switches.  The other extreme is just to tie all the grounds together strongly with multiple vias at every loacation.  In our work, we really don't have to deal with those types of system grounding issues, so our layout guidelines are just "snapshots" of that local sub-circuit.

As far as SS is concerned, there is an amount of DC current required to charge up the output.  With a linear slow start ramp, that extra current is i = Cout * Vout/slow start time.

So longer slow start reduces start up current for the circuit.  Technically, "start up current" would be more correct.  "Inrush current" usually refers to the extra current drawn by completely discharged electrolytic capacitors when voltage is first applied.  In any case, there is an additional current required at start up, above the actual load current. 

I think I posted to another thread on this, but I would be inclined to think it is the SS/ENA pin of the TPS54616 that is pulling down the node.  We have seen instances wher excessive negative excursion on PH can cause SS/ENA to reset.  In many cases, moving the input bypass capacitors closer to the IC and directly connecting them to the VIN and PGND pins can reduce or eliminate this effect.  To test it, you can completely disconnect the PWRGD pin from SS/ENA and see if SS/ENA still resets during start up.

John:

thnx a lot.

Your are spot on regarding the "start up current".

On this I fully agree: & indicated as such by saying rate of (v/L)dt will be high.

So far all is in good  order!

We have spent umpteen hrs pushing typing buttons debating tarce/track/single track AGDN.....on & on.

What you say about system level grounding is also right on.

In this case, we have I think 9 TI chips each with AGND & PGND, 4 DDRs, 4 gig-bit rated processors ,FPGAs  etc etc.

& all run quiet due to extensive use of ground  planes.

thnx again.

-robin

John:

I  cannot get back to your postings on this...how do I do that?

In any event, our fix for preventing oscillations at SS/ENA pin between 1.5V  using TPS54613  & TPS54616(3.3v)   did not totally solve the issues. We used 68k to pull up 56613 PGOOD to 54616 EN.

You had proposed that if PH pin of 54616 is below a certain level of  GND, then SS pin might oscillate.

How  probable is this? Bear in mind that we have > 100 assy in operation, no issue at any temp ...excepting when we go down to -25 deg C.

Would it be temp dependent phenomenon?

& only is some cases?

Is there a way to set up this  section to force into oscillation & then find the root cause? Could it be that a few bad apples in the lot we bought causing this & all we need to do is to replace them?

Could we set up s test to weed out such suspect population?

I am working from memory here.  It has been a few years since we looked at this.  The root cuase is the reset of SS/ENA is due to extra-Hi spike in nodes of a bandgap current generator in the Bandgap_pg2p0 block (an internal circuit block in the fault detect circuitry). 

thnx a lot John.

Let us see if moving the cap does it.

-robin