We are trying to calculate the optimum values for the compensation networks. We ran into a few of questions. We are using two UCC28070 ICs in parallel for our design (very similar to the schematic on page 20 of the datasheet). As stated on page 19, we have combined IMO and VAO. It says to "adjust the calculated impedance by 1/2". For IMO this seems pretty straightforward. I just calculated Rimo as through there was only one UCC28070 and it only supplied half the total power, then used half that calculated value as the actual Rimo resistor. However the VAO isn't just a simple resistor+current source. Am I supposed to calculate the comp network for one UCC28070 at half the total power again, then reduce the resistor size by half and double the capacitors?
My second question is about the current loops. I've been using the TI UCC28070 Design Tool excel spreadsheet for the CAOx current loop network, but there are several things that seem strange. I downloaded the spreadsheet without changing any values and the Current Loop Frequency Response graph is very surprising. Its crossover frequency is 1/10th the switching frequency, which is not surprising, but the phase margin is very surprising. There is maybe 40-degrees at the crossover frequency and much less at lower frequencies. The phase doesn't peak until it is 2.5 times higher than the crossover frequency. Is the ideal phase graph different for this inner current loop versus most comp networks (like the VAO comp network)? Or is this just the best phase margin you can get in this situation?
Another thing that seems off about Equation 24 on page 30 of the datasheet, states that Rzc should be less than or equal to =4*NCT/(10*(100*10^-6)*DIL*RS) which comes out to 2701 ohms in the design tool spreadsheet. But they set the Rzc resistors to 55601 ohms. It looks like they just calculate the resistor to be 1/10th of the switching frequency. But both in their example design and our design, equation 24 seems to be the limiting factor. We would select 3kHz but the highest we can obtain is 930Hz if we obey the restrictions of equation 24. I can't really make sense of much of the information on the current loop design. Any help would be appreciated.
My final question is about externally synchronizing three phases. Can the PWM clock provided to the UCC28070 IC be set to run the two phases at an offset other than 180 degrees? For example, to run both phases at 50kHz you would provide a 100kHz clock (1 pulse every 10 microseconds). But could you use 6.67us for every odd pulse, and 13.33us for every even pulse, so that the two internal phases in the UCC28070 would be running 120 or 240 degrees out of phase with each other instead of 180? Or does the UCC28070 have some internal need for both phases to be 180 degrees out of phase.
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