EMI issues with POE (TPS23754PW)

Please refer to application reports on the product folder:

http://www.ti.com/lit/an/slua469/slua469.pdf

http://www.ti.com/lit/an/slua454/slua454.pdf

Hi Eric,

Our design is refer to http://www.ti.com/lit/ug/slvu301/slvu301.pdf, and I did modify a board according http://www.ti.com/lit/an/slva475/slva475.pdf, but it looks worse. Is the efficiency is the purpose of updated doc? What are critical things will affect EMI? I try to adjust the value of Gate resistor, BLNK resistor, but no change on EMI scan.

Thanks,

Gorlic

How about the PCB layout (# layers, routing, spacing, GND planes, etc.)? The input filter is very critical and you may have to add common mode choke.

Hi Eric,

We did layout with 4 layers board, but all parts on top side. We tried with common mode choke, but it just cut down the noise between 10-30M (that's what we expect based on the previous test), but it won't help with the harmonics of the 250k noise.

Thanks,

Gorlic

I'll investigate more next week and get back w/any ideas.

To clarify: slvu301.pdf is just the TPS23754EVM-420 user guide. This EVM is built on a 2 layer PCB and does not contain the EMI recommendations covered in the suggested application reports for EMI/EMC control (http://www.ti.com/lit/an/slua469/slua469.pdf and http://www.ti.com/lit/an/slua454/slua454.pdf).

slva475.pdf starts with the TPS23754EVM-420 described by slvu301 and increases the efficiency (which may as you've mentioned make emissions worse on this non-EMI optimized 2 layer PCB).

Hi Eric,

Were are behind our production schedule since the EMI issues. Can you or someone else help to look into our schematics and layout, then give some specific suggestions?

Thanks,

Gorlic

With reference to the TI design in SLVU301, please consider the following:

1. Increase C24 from 2200pF, 2kV to 4700pF, 2kV and also add another 4700pF, 2kV capacitor across the isolation boundary from output GND to T2-1. We're trying to improve the common mode filtering. But in addition to CM capacitance we'll need a fairly large common mode inductor such as ~2mH for a sufficiently low corner frequency.

2. Add or or increase the capacitance provided by C10/C11 if possible?

3. Make L1 as large as possible.

4. For layout, please refer to the guidelines from the attached application report (starting at pg 3.

 We design wlan AP with TPS23754,  you can adjust the caps across the isolation plane, position and capacitance.

  The common choke is important, you should choose one with high common impedance ( 5k~ ) at 200K~1MHz.

But when Wlan AP is in link state, 30M~100M is  over the limit. We adjust the gate resistance,RC snubber...but they were not very effective... Could you give me some advice?

Thanks

Eric,

1. What do you mean by common mode inductor? FB3 & FB4?

3. You mean increasing 3.3uH to higher value, right?

Questions:

1. Can 2nd MOSFET be replaced with a Schottky Diode?

2. I tried to input DC from VDD side (jumpers on VDD, VSS, J8), but it won't work. Any ideas?

Thanks

Any update Eric?

Thanks,

John

Here are replies to Gorlic's recent questions Have the layout guidelines in the application notes been followed and if so, were they helpful?

1. What do you mean by common mode inductor? FB3 & FB4? I was referring to L2 in the SLUA469 application report (schematic pg 2). A secondary common mode filter for the higher frequencies using ferrites/caps is also recommended.

3. You mean increasing 3.3uH to higher value, right? Yes, a bit larger but such that it can still support the dc current.

Questions:

1. Can 2nd MOSFET be replaced with a Schottky Diode? The switching currents can be quite large and sometimes too large for a diode operating at 5V, 5A output. What is your maximum output power?

2. I tried to input DC from VDD side (jumpers on VDD, VSS, J8), but it won't work. Any ideas? This configuration should work as you've described. What was the dc input voltage level applied? For the EVM settings the dc input voltage should be above ~40V to turn on. If you need the EVM to turn on at a lower voltage R6 value can be increased.

Hi Eric,

Max current of our product is around 4A at 5V. So is that possible to replace with a diode, or just adding a diode in parallel across it to take up the slack should the turn on or turn-off timings be slightly off.  By itself the diode is less efficient, but Q3 would short it out when it turns on.

I am using a 24V according the note: External Adaptor: 24V & 48V

C22 and R16 act as a snubber across Q1 to damp the effects of parasitic capacitance in the FET body and parasitic inductance in the leads/pads/traces, toying with their values may yield some benefits? If yes, any suggestion?

Also, it doesn’t appear that the evaluation board circuit has any snubber components on the primary side FET as mentioned in SLUA469 for their older part.  Could you suggest values for a resistor and capacitor to be placed across Q2.

Again, can you or someone help to look into schematics and layout?

Gorlic, I looked back over this thread and do not see your schematic file and layout. If you don't want to post it here, you can send it to TI through the distributor Arrow. Or just attach it to the thread. My responses below are with respect to the TPS23754EVM-420 (SLVU301 EVM User Guide).

"Max current of our product is around 4A at 5V. So is that possible to replace with a diode, or just adding a diode in parallel across it to take up the slack should the turn on or turn-off timings be slightly off.  By itself the diode is less efficient, but Q3 would short it out when it turns on." The "parasitic" diode of Q1 is oriented in the proper direction to conduct when Q1 is off. If Q1 were replaced with a schottky rectifier, at least a 10A diode should be used. But, I don't see how this might help the EMI issues.

I am using a 24V according the note: External Adaptor: 24V & 48V Will your adapter be inserted between VDD-VSS or VDD1 and RTN (see adapter ORing options in SLVA306A)? There are advantages and benefits to each as described in the TPS23754 datasheet and SLVA306A. If you choose option 1 (between VDD and VSS) and need 24V adapter operation, then R6 on the EVM should be changed so that TPS23754 UVLO starts somewhat below 24V (see pg 10, EQ 5 in the DS).

C22 and R16 act as a snubber across Q1 to damp the effects of parasitic capacitance in the FET body and parasitic inductance in the leads/pads/traces, toying with their values may yield some benefits? If yes, any suggestion? Look at the switching waveform with a scope. Ideally, the snubber should suppress the spike within a few cycles (main spike plus maybe one more smaller wave).

Also, it doesn’t appear that the evaluation board circuit has any snubber components on the primary side FET as mentioned in SLUA469 for their older part.  Could you suggest values for a resistor and capacitor to be placed across Q2. The EVM uses a "clamp type" of snubber formed by D15, C12, R12. This protects Q2 Vds but is mostly non-dissipative for efficiency. You can try also an RC from Q1-D to RTN. Again, choose values to snub the ringing within a few cycles.

Hi Eric.  I'm working with Gorlic on this design and have read over many of your application notes, as well as the EDN articles "Boost Efficiency for Low Cost Flyback Converters" and "Benefits of Adding an Active Clamp to a Synchronous Flyback Power Supply" by TI engineers John Betten and Brian King.  While SLUA593 focuses on the efficiency gains of the alternate input bridges, I notice that it shows a different evaluation board that makes use of an active clamp rather than an RCD clamp, and has a layout more in line with the recommendations of SLUA469.

Is that demo board available?  Are its conductive emissions better than those of the TPS23754EVM-420, and would implementing it's active clamp circuit rather than the RCD of the -420 design be worthwhile in our situation?  Thank you.

An active clamp converter (forward or flyback) can provide better supression of the high frequency ringing during switch dead time. The author of SLUA593 also authored both of the referenced EMI/EMC control application reports and would have followed the same rules/guidelines for the SLUA593 design. I do have the design files for SLUA593 if you need them, but there is not an available demo board (unfortunately).

There is another TPS23754EVM (-383) which has a better layout and follows the guidelines. It is an active clamp forward converter at 12V output. The changes for a 5V output are fairly minor and I can provide a schematic if necessary. TPS23754EVM-383 was scanned for conducted emissions and the plots are in the EVM user guide (http://www.ti.com/lit/ug/slvu304c/slvu304c.pdf).

Hi Eric,

Thank you very much.  We were back at the lab yesterday and tried out a number of things and ultimately got passing measurements on conducted and radiated.  Increasing the value of the capacitor across the isolation barrier to 4700pF reduced the conducted 250KHz and associated harmonics to acceptable levels, choke coils at the adapter and PoE bridge inputs helped higher frequency conducted issues, and an RC snubber across the primary switch FET fixed radiated issues.

We saw on an oscilloscope connected to the drain of the primary switch FET (Q2) that the RC snubber causes some crazy low frequency ringing on the trailing edge of the pulses, the effect was extremely bad at light loads.  We used the same values (1200 pF + 10 ohms) as the components on the secondary FET (Q1), but have since noticed that the circuit for your older PoE chip in SLUA469 uses lighter values (330 pF + 82.5 ohms).  I'm guessing that we should have used those instead?  We have a pass in our pocket now, but I worry about whether or not that low frequency ringing will have other effects like increased dissipation and shorter lifetimes...

We'd also like to try the active clamp configuration, if you could send me the SLUA593 design files I'd really appreciate it.

Thank you.

Could you send the Oscope plots? I've attached the design files to support SLUA593. Note that there are 3x design file sets. 69 is the main design file set for the main board and there are two others for the bridge daughter cards.