1) According the Table 6, there should be 500-550usec delay between the PWRON signal going LOW and the INT1 pin activating. We are seeing ~500msec. Was this a typo in the datasheet? Or are we not setting something up properly?
2) Our desire and understanding is that INT1 pin interrupt can be activated by a falling edge on the PWRON pin. However, if we keep the PWRON pin LOW after the initial transition and we acknowledge the interrupt, INT1 is re-activated. Which suggests it is not edge triggered but level triggered. Which behavior is correct?