TPS54260 For GSM Cell Modem

Can you tell me what your load steps and slew rates are?  Are you crossing DCM/CCM boundaries and or eco-mode boundaries?  High slew rates and steps that cross the DCM/CCM or eco-mode boundaries will result in worse transients.  They are difficult to predict from equations.  Can you post waveforms?

John

I started out doing 0A to 2A but realized that would probably not be a good test becuse of the eco mode.  I then added an always on load of 0.15A and used the MOSFET to switch in power resistors.  I looked at both 0.15A to 2A step and and 0.15 to 2.5A.  I mainly focused on the 2A step since that was already not as good as expected.  I'm not sure about the slew rate though.  I used the MOSFET test suggested in the TI app notes on transient and compensation improvement.  I have to find a card reader since my scope only saves to CF cards - The responses don't look too bad in terms of any ringing or slow recovery.  A 400mS pulse recovers around 150mS an there is no ringing, just the ~180mV under\overshoot.

Christopher

You will proabaly want to take a close look at the slew rates.  1 A / usec is usually considered "fast".  If your slew rate is near or faster than that you may find significant voltage deviation.  Since our reference designs do not have any specific load step requirements, we often use 100-500 mA / usec slew rates (what I would consider "medium") to show better transient response.  You will find that fast trainsients can require significant amounts of output capacitance to maintain small amounts of voltage deviation

John

Thanks, I will look at my slew rates and compare them to the GSM app note.  Maybe I'm overengineering\over-expecting....  I'll also see if I can get some scope captures in the next couple of days after I work out getting a measurement across a current sense resistor.

Could you comment on the comp calculations for using electrolytics if I have to?  As I said before I am not sure I want to use ceramics greater than 47uF because of my concern on cracking due to out door use.  So far my experiments with a low ESR 2200uF cap gave me a much noisier (fine ringing) on a transient.

Thanks

Christopher

My preferred method for compensation design uses pspice modeling.  That way I can accurately estimate the overall power stage gain and phase characteristics and design the compensation network accordingly.  I'm not sure if there is a published average model for TPS54260 as I do not actually support that device.  If you have access to a network analyser, you can estimate the compenstaiton using the datasheet equations, then measure the loop and fine tune as required.  The doewn side of 2200 uF is that you will likely be limited in your loop BW.  The power stage gain will be pretty low at higher frequencies requiring a large value for the series resitor from COMP to GND.  That resistor will interact with the output capacitance of the error amplifier to produce a pole frequency that is lower than normal, reducing the available phase and forcing a lower crossover than can be obtained with a lower value output cap.  As always, it becomes an engineering trade off.  There is no "free lunch" 

John

I do not have a network analyzer.  In general (as a digital\firmware guy masqurading as a power guy) I have to rely on datasheet calcs, app notes and maybe SwitcherPro.  Other than the potential cracking issue, I think the ceramic approach with around 300uF will work.  I'm just trying to understand the design starting point for an electrolytic better as the DS and app notes seem to have 1/2 info on using those larger ESR caps.  I only started with the 2200uF as I had them in house.  You had mentioned around 680uF to another customer also working on a GSM supply.  I'm assuming that would be with a an electrolytic?  Nichicon has some conductive polymer caps with low ESR, that's one line\type I was thinking of if I have to go to electrolytic.  Do those look like a good alternative for larger value caps?  Also should I send an email specifically to someone that directly supports the TPS54260?

Thanks again!

Christopher

The main difference for electrolytic caps is the location of the ESR zero.  For ceramic caps with ESR in the 1-3 mohm range the ESR zero is above the frequencies of interest.  For higher ESR, teh zero frequency is lower and changes the slope of the power stage gain from -2 to -1 and also introduces phase boost.  So in general it is easier to compensate.  If the value of Cout gets big, teh dominant pole frequency is much lower and the gain of the power stage is lower at the same crossover frequency and requires more gain from the compensated error amplifier as I outlined previously.  I think the 680 uF was probably a POSCAP type with around 25 mohm ESR.  That puts the ESR zero around 9.3 kHz which will give good phase boost if you want to cross over in the 50-75 kHz range.  I'll alert one of my associates to look at this forum thread.

Hi Chris,

Do you have a schematic of your current design you can share?

Either an electrolytic or POSCAP are good choices for the bulk capacitor. One thing to make sure you account for is any variations in the electrolytic over temperature and operating conditions which can affect your control loop.

Like John mentioned what is likely happening is your loop bandwidth is becoming the limitation with the large output capacitance. The pole of the modulator is becoming such a low frequency you need much more gain from your compensated error amplifier to increase your bandwidth.

I do not have a PSPICE model readily available right now. Because you are using such a relatively small ceramic capacitance compared to the electrolytic a good starting point when selecting your compensation components would be to ignore it completely. I would use SwitcherPro's small signal model to get an idea what the loop response looks like.

Another option to improve your loop bandwidth further, is to adjust your compensation resistor and see the effects on the transient response. Increasing the resistance of the compensation resistor (R4 based on the datasheet equations) will increasing the gain of the compensated error amplifier and your loop bandwidth. As you increase the resistance your phase margin will also begin to decrease. When you begin to see ringing in your transient response you will know the phase margin is below 45 degrees.

Regards,
Anthony