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Hot swap LM25066 Short test problem!

Randy Wang
Intellectual 1705 points
Other Parts Discussed in Thread: LM25066

Hi,

  A customer sent me some waveforms about short test, I found it's strange compared to our LM25066 datasheet. Input voltage is 12V, Timer set to 4ms, the OCP set to 83.33A, and circuit breaker set on 1.8 times.

There are some problems blow:

(1) When have short test by E-LOAD, the gate shut off the mosfet, but not completely, there still have current until the Timer reaches to 1.7V. Why?

(2) When have short test by E-LOAD, the VIN drop down to 11.2V, is that normal to usual case?

(3) When have hard short test, the Fault & Timer didn't rises immediately, and the gate slow opened after shut down. Why have these waveforms? 

 5342.Waveforms of LM25066 Short Test.docx

Thanks,

Randy

 

  • 0
    TI__Prodigy 20 points

    Hi Randy

    Please see my comment to each of your problems accordingly.

    1) The fault time allows the part to operate in current limit or power limit until the timer cap voltage reaches 1.7V. I believe the current you were seeing after Vout dropped to zero to the point when timer cap hits 1.7V is for the power limit. Please note that during this power limit, VDS is approximately 12V when the output is forced to zero, so the current threshold under power limit condition can be calculated out based on the Rpwr you have in the design.

    2) The Vin drop should be related to the parasitic inductance in your input line. When a huge current spike presents to the line, it will induce voltage drop. You need to confirm if this point of measurement is right at the VIN of LM25066. And if it is so, you should see the same drop when doing a hard short.

    3) When implementing a hard short at the output, the part will immediately shut down the FET as responding to a circuit breaker event. (You can see the current is roughtly 180A in the waveform.) Timer is responding immediately by charging its cap; however, as the current path is cut by the shutting down of the FET, voltage across the Rs falls down below its threshold and notifies the timer of the end of fault event. So you could see a slight discharge at timer cap together with the GATE voltage increase, which is followed by a linear region operation of the FET in power limit condition since the VDS is still pretty high. In this power limit, the current is adjusted around 20A as observed in the waveform and the timer charging process is going along with it.

    Further more, as to address the previous question you asked the other day about why the current limit is around 105A instead of the set 85A. Please take a look at the Vin in the first waveform. Your Vin has a voltage drop during this current limit, which will result in a reduced measurement on your Rsense voltage comparing with the normal OCP in (12V-Vsense), and that is how you get the error.

    You may ask your customer to check the E-load and verify his layout of design, and read the datasheet for more understanding on current limit and power limit. :)

    Thanks.

    BRs

    Serena