Good Layout guidelines of switching regulators is well described in may places. Some of the wisdoms are:
.)Keep the large di/dt away from the gnd plane and in a small loop (Red lines in drawing below)
.)Have a common signal gnd and power gnd at one place.
.)Keep the switching node within a small area.
... and so forth. Good references are for LMZ10500: (http://www.ti.com/lit/ug/snva491a/snva491a.pdf) and http://www.ti.com/lit/ds/symlink/lmz10500.pdf
This is all very well and you can get demonstration boards where all this is nicely done according to the books (but rarely with readable layout plots which really shows the important details - this is however not my point here).
The real challenge begins when system design and layout starts:
In most pcb's you have numerous power rails - some driving digital and some analogue loads. The concept of single star point gnd becomes imposible and a separate isolated main power source for each regulator is not practical.
If you use the WEBENCH to design your FPGA supply for instance - this is typically the scenario you will get.
Now how to deal with that? This is my question for which I request inputs. I have some ideas, but would really like them challenged.
I have attaced a drawing below illustrating a typical system: Many voltages, some switchers (could be LMZ10500), some linear (could be TLV70718). Extended ground plane. And most importantly: Only one power source.
Because there is only one source there will be current in the gnd plane crosstalking between the different loads. In order to lower the high frequency component of this GND current resulting from the buck converters in particular, I was thinking of adding inductance (lossy ferrite) in series with the switcher input as illustrated in the drawing.
By placing the main power and the more sensitive analogue part in oposite ends (as indicated on the drawing) one avoids to have the swither residual currents running through the gnd plane where the analogue parts are. Spurious currents in the gnd plane gives difference in potential which usually is bad.
Note that there _will_ be a gnd potential in the analogue zone (Vn) due to the return currents in the gnd from the other supplies, BUT this will be a common mode potential and typically of less severity in an analogue circuit, except when it comes to dealing with the analogue IO to the board - then it is a problem.
Also note, that you dont always have the luxury of placing your analogue and digital components at will - example is an FPGA which holds some noise sensitive PLL supplies.
Can you comment on these ideas - does this look like a good plan? Links are also welcome. I know this is hard to be very general about as there are many contraints - but it is a real world problem most designers face but which is not very often adressed.
Thanks for any comments.
Henning
