hello, as the topic when i develop the 6670 board, I found that the smart reflex power CVDD is not right.
when i configure the output power 0.8V, it is. and it doesn't change following the VID signal.
I think it's not normal.
in addition, I set the cvdd to 1v, and control the power sequence through the FPGA,
the signals in the FPGA is ok and correct, but the resetstat pin of the DSP is always low,
I feel the dsp is not request the signal external.
now i don't know how to do and the teminal time is very closed.
please give me some advises , thank you