BQ77908A configuration file (*.cfg) format

The easiest way to get a working format is to connect to a part and save a file.  Then you can edit the file to generate multiple files

In general it will ignore blank lines or treat any line with a semicolon as a comment.  So you can't have in-line comments, but you could add a comment line or lines above or below the value.  Registers and data are in hex on individual lines with a colon in between.  An example from a saved file is below, this may not represent a suitable working configuration:

; bq77908 Register File
; 1/27/2012 9:52:11 AM
01:4C
02:39
03:42
04:C
05:C1
06:10
07:F
08:0
09:F0
0A:F3

Thank you!!!

The file is loading properly now that I have the correct format.

Now I am experiencing a "Program Failed" message.   I note that the ZD pin is strobing a momentary voltage (using DVM) [I need to get a scope at my office desk where the programming software is installed], but the PGM pin does nothing (0V continually) which means that the 14V programming voltage is not being gated to the EEPROM pin of the BQ77908A.  Is there any explanation on the operation of the programming interface protocol, e.g., is ZD supposed to stobe which is what I would expect the PGM pin to do???  Does the data get written and then read for validation?   What is the nominal clock clock rate for ECLK?   The header diagram of the EVM schematic on page 30 of the EVM Evaluation Manual shows pin 1 in the upper right corner whereas when looking at the header from the top of the EVM and my design, pin 1 is at the upper left, i.e., the diagram appears as if the header is being viewed from the bottom.   I connected the header pins by their name (pin number) and not by their represented location on the page even though the odd and even pins appear swapped? 

The programming interface circuit I have constructed is a clone of the EVM schematic on page 30; I did not include the three-terminal header marked "Install shunt for test" as the EVM instructions indicate to remove this strapping option.   The ZD pin is pulled down with a 100K ohm resistance so there is little load on this pin.  There is no separate driver on the ZD signal.

I have used different USB_TO_GPIO pods, different programming modules, and different target boards with no success at programming.   Since I did not have room on my target board for all the programming components, I placed the J2 (2-pin header), J3 (10-pin header), Q1 (BSS84), Q2 (BSS138), C1, C4, R1, R2, R6, R8, R9, R10, R13 and R15 on one PCB and via a 5-pin interface (EEPROM, ZD, ECLK, EDATA, GND) placed the other programming interface components on application PCB so that pulled downs and zeners would be present on the open signals of the common 5-pin interface when disconnected from the programming module. 

Any suggestions as to what I may be doing incorrectly?

Thursday morning update.

Now that I have a scope I can see the ECLK rate of about 50kHz, but I am only getting what appears to be only 6 clocks pulse trains of 9 clocks each (3.3V in amplitude), but I would assume I should see at least 10 pulse streams, one for each of the 10 programming values.  The clock pin does appear to be correct (9 clocks), so I believe my header connection is not reversed (odd for even) as I first expected.   The ZD strobe is 43mS in length with an amplitude of 3 volts.  The PGM pin from the USB-TO-GPIO pod does nothing (0 volts continually).   The EDATA trace does appear to be data with the first byte being 0x20 (ASCII space) which does not correspond to any of the data from the file and not the first entry of 0xcc which I may expect unless the protocol has some preamble associated with the data sequence.   If the ninth clock is an ACK, it is high which means NACK if the protocol follows the SM Bus methodology.

Hope this additional info helps.    Thanks for your assistance.

Programming is sucessful!!!   Thanks!!!!   The "gotcha" was that I did not have the CHGST pin pulled to PACK+ via a 15K resistor during programming.  The programming instruction (SLUA648–July 2012) indicates "Before running software, some hardware connections must be made to assure the necessary signal can be applied to the specific pins of bq77910 or bq77908 from the USB-TO-GPIO tool kit, for details on which signal should connected, refer to schematic of bq77910EVM in document  sluu368."   The required connection to CHGST is lost in the schematic, but for future releases a reference to Figure 3 would be helpful.

For testing I "reprogrammed" the over-current discharge, over-current charge and short-cicuit discharge to the minimum values of 5A, 8A and 2A, respectively based upon the 5 mohm sense resistor being used   See registers 8 and 9 below.  The ISNS_RNG bit is 0 in register 7 (bit 5) . 

01:CC
02:26
03:52
04:6
05:C4
06:4
07:F
08:00
09:F0
0A:ED

However, upon testing we could could charge at 3, 4 and 5 amps and discharge at 6 amps without protection being invoked (we need to improvise to get a controlled short circuit current as our load box is maxed out).  We measured -15mV across the sense resistor during the 3 amp charge sequence.  Any ideas as to what we did wrong?  Are there any special procedures in reprogramming the device with new values?   Is there any way to read the register values after they have been programmed?

Thanks again!!

Glad you had success, and thanks for the suggestion.  The programming software associated with SLUA648 does assume a familiarity with the part typically gained from using the evaluation GUI and boards, sorry for the confusion.

A scope may be very handy for looking at the current protection behavior also.  Be sure the part is not protecting and recovering so quickly that it is not apparent.  Refer to table 2 of the datasheet or other detailed descriptions.  For example SCC will recover with CHGST low.  Also see http://e2e.ti.com/support/power_management/battery_management/w/design_notes/1380.aspx 

You can apply a voltage from a supply through a divider to the sense inputs for initial checkout or a low voltage supply across the sense resistor or battery- to pack- current path.  This lets you do initial checkout without the high wattage power supplies and loads. Zero delay mode (ZEDE high) may help see trips if you think the load may not be constant, but it will also allow trip from noise.

For long term data retention the number of programming cycles is recommended limited to 3, see the datasheet. In evaluation you might write a part many times, but may not want to put that part in the field. When you write register 0x0B back to 0x00 in the programming sequence, you can read the EEPROM values from the registers 0x01 through 0x0A.  The evaluation software will do this, not certain about the programming software.