TPS2491 - Using parallel FETs

http://www.ti.com/lit/an/slua500/slua500.pdf describes a 100A, 12V HS.

The large capacitive load will enforce a lot of heating during start up. Keeping the FET(s) cool using heatsinks or fans will probably be required. BTW, there is a design spreadsheet tool that can help with the calculations (http://www.ti.com/tool/tps2480-81-90-91-92-93_calc) and will drive a safe design including start up and SOA.

Just in order to support the dc operation, I would expect that at least 3x CSD18501Q5A in parallel would be required along with significant cooling to start up the circuit with the large output capacitor.

What calculations are you using to determine the number of FETs required.  My total power required is 800 W.  I am thinking about using infineon's IPI024N06N3 N-channel FET with a 2.1 mOhm Rds on.  It can dissipate 250 W.  So, 800 W / 250 W = 3.2 or 4 FETs.  Is this the logic that is used to determine the number of FETs.  If so, it does not hold for the provided example based upon the International Recitfier part.  Can you advise?

Thank you,

Noah

The process is detailed in the spreadsheet tool that I sent the link for (on the Intro tab). That being said, I tried your scenario and believe it would be difficult to achieve a safe startup with such a large output capacitance. Did you really mean 33000 uF (33-mF)? Normally, with smaller output C you can take advantage of the FET transient thermal impedance to allow safe start up. But with such large C, the turn on time is too large to use this. The basic idea of FET power selection is to ensure that the junction temperature does not exceed the ABS MAX (with a ~25C pad) during start up.

The spreadsheet is attached using 3x of the IR FETs (RED cells will help indicate the issues). You can tweak any of your other param's for which my assumptions were wrong.

Eric,

I fundamentally do not understand the numbers in the spread sheet, and how these contribute to the FETs' performance.  First of all, the IR FET has an Rdson of 3.3 m-Ohm.  So, 3 of these in parallel would yeild 1.1m-Ohm for the combined Rdson, not the 0.7 m-ohm, which is in your spread sheet.  Furthermore, Rdson only comes into play once steady state is acheived.  How does it contribute to the trasient power handling of the FET?

I do not understand what is gained from using mulitple FETs in parallel, and how these gains are quantified.  Aside from reducing the Rdson, and increasing gate capacitance, what other parameters are improved?  Is the juntion-to-ambient resistance divided by the number of FET employed?  It is unclear what design goals are being met by using mulitple FETs.

My goal is a robust solution. I'll use as many FETs as needed, but I need a quantifiable means to demonstrate that this design will be able to handle the 33mF load, and supply 33 A of current (worst case) steady state.  I've read the application note on the 12 V 100A solution, and still do not understand the justification behind selecting 5 FETs.  Why wasn't it 4?  Why wasn't it 10?  I need to know how many FETs will be needed to make my solution work.  Insight into this factor is needed. 

Thank you,

Noah

My mistake; I meant 3x of the Infineon FET (IPI024N06N3) which is 2.1mohm at Vgs=10V. You are also correct that the Rdson dominates power dissipation during steady state operation. Steady state is the easiest condition to evaluate based on junction temperature. If your Tj is too high, then add additional parallel FET's to yield a junction temperature with margin based on your PCB thermals and system operating temperatures.

For non-steady state operation the problem is much tougher as you cannot guarantee sharing across the parallel FETs. It might be more straightforward to read the design example in the TPS2491 datasheet (starting on pg 14) to better understand how to set the FET power limit and how that relates to your load capacitance.