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TPS40210 PowerPad - Must it be grounded?

Other Parts Discussed in Thread: TPS40210

Got another question regarding the TPS40210 and I couldn't find the answer using the search function.

Does the PowerPad have to be grounded or can it be soldered to a logic level network with wide traces (for heat dissipation)? Specifically, in my application, I could substantially improve the layout if I soldered the power pad to the network of traces that control the EN/DIS pin on the TPS40210. 

Additionally, if a different method of heat removal was provided, would it need to be grounded? E.g., on a prototype board that was to be hand soldered, could I put a dab of thermal compound between the copper trace and the PowerPad and assemble it that way? Or perhaps a dab of thermal compound and a heatsink above it?

Thanks!

  • Tom,

    I don't think you need to be concerned about the powerpad. This is just a controller.

    I did some rough power dissipation calculations with Vdd=24v, & fsw=500KHz (refer datasheet page 20)

    Pq = 24*1mA= 24mW

    Pg=24*13nC*500Khz= 156mW

    Pe (this will be zero if you don't have any load connected at BP pin)

    Total Pd = 180mW

    This is negligible. MSOP 10 package without a powerpad can easily handle this. ThetaJA of MSOP10 is 160

    Pd = 150-75/160 = 0.46W

    ThermalPad can be connected to copper, other than ground. If you connect to traces, I don't think it will make much difference, since the pad is already connected to package leads internally, thru which some heat is dissipated.

    Ground is recommended, since ground planes are common in PCB.

    Don't forget to read SLMA002 and SLMA004 app notes.

  • I hope that is the case. I wasn't worried about the PowerPad until I read a another post on here regarding a different controller. The post seemed to suggest that leaving the pad ungrounded could result in an (electrically) noisy chip.

  • Hi Tom,

    With the TPS40210 this is of relatively low concern because there is no purposeful electrical connection to the ground pad internally. The concern here is more the heat dissipation. Typically this is not an issue unless you plan to operate with high VIN and high switching frequency. This increases the loss of the internal regulators (high vin) and the gate drive losses (high fsw).

    On a general note the concern we have with the internal FET regulators if it is not grounded is typically do all of our evaluation with the power pad grounded as this results in the best thermal performance. Although there is no connection it is a variable we have not changed so we cannot always say with full confidence the performance will not be affected.

    Regards,
    Anthony

  • Tom Schmit said:

    I hope that is the case. I wasn't worried about the PowerPad until I read a another post on here regarding a different controller. The post seemed to suggest that leaving the pad ungrounded could result in an (electrically) noisy chip.

    Tom, which post are you referring to.

  • Hi Anthony,

    I am seeing some strange behavior with my TPS40210 application. Can you please take a quick look at the two questions below please?

    I am debugging some issues with a 10Vin -> 24Vout, 2.4Aout boost application design using the TPS40210 PWM IC. I have two issues that I cannot debug and need some help.

    1. The design exibits some symptoms that per pg 15 of the datasheet sounds like it might have some Sub-Harmonic Instability. My design alternates short and long pulses after leaving DCM. When viewed on the O-scope it appears to have "jitter" at the switch node. However, per the calculations on the datasheet equations (8), (9), and (10) the design should not operate and exhibit these symptoms.

    Vdd = 10V, L = 4.7u, Fsw = 515k, Vout = 24V, Vd = 1V, Vin = 10V

    Rsense = 0.005

    Rfb = 30.9k, Cfb = 5.6n, and Chf_bp = 56p

    2. Grounding of the thermal pad to a signal ground helps to minimize this issue, and the pulses are almost identical. The thermal pad is not called out as electrically connected. Why would connecting this pad to ground help to minimize the "jitter" on the switch node?


    Any insight into what I may be dealing with here would be greatly appreciated! :)

     

    Thanks,

    Marshall

  • Check the Feedback node and Vout node. 

    Do you see noise at feedback node?

    How did you select the inductor value. Did you calculate it.

  • Thanks for the reply. There is some noise on the FB pin but, it lines up with the switch node, not sure which one is leading who there...

    I selected the inductor from the TI web-bench for the controller. I knew that the ripple current was higher but, I thought that the efficiency would be better in DCM mode. But, my design is quite noisy.

    We changed the Rdiv highside value for DAC control reasons. The TI Apps engineer recommends that I recalculate the Rfb to lower it's value. Although the datasheet calculates it as increasing with R1. I was pointed to check the gain and phase margin for the new values using a model for the IC. I'll follow up to let you know how it turned out.

    Thanks!