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LP3972 with PXA270

Rak
Intellectual 505 points
Other Parts Discussed in Thread: LP3972

Hi,

My customer would like to know how LP3972 can be connected to Marvell's PXA270.

Do you have example connection diagram of "PXA270 and LP3972" ?

{expecially, he wants to know... 'where to connect nVDD_FAULT of PXA270' and 'how to control 3 VDDs (Core, PLL and SRAM) by PWR_EN (BUCK1, LDO5 and... ???)'}

Thank you in advance for your help.

Best regards,

Rak

 

  • 0
    TI__Intellectual 1955 points
    • Subject:     LP3972 PMU interfaces with PXA270 Apps Processor:                                    From: Kern Wong
    •                                                                                                                                                               Apps Engn, TI SVA
    •                                                                                                                                                                Nov. 9, 2012                                                                                       

    Rak,

    Please communicate to your customer to review Marvell literatures online such as listed-

    http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_emts.pdf

    http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_design_guide.pdf

    http://www.marvell.com/application-processors/pxa-family/assets/pxa_27x_dev_man.pdf

    Unlike Intel it seems Marvell has in some cases not provide the qualified vendor part information in references I located, as the LP3972 is a qualified part working with the PXA27X processor and SS equivalents.   I am including herein some drawing to answer your questions on which regulator is known to be used on what block and the connection of the nBATT_FAULT line.  Please consult Marvell for up-to-date information and advice.

    * Diagram below depicts regulators in the PMU typical interface to various block in the PXA27X processor: (see image attached)

    Table 8 shows some general interface info between the PMUIC and the processor:  (see image attachment)

    Figure 14 show a generic connection of the nBATT_FAULT connection between PMUIC and Processor:  (see image attachment)

    Figure 5  is another generic block diagrm showing nBATT_FAULT connection between the devices:  (see image attachment)