This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

strange H-bridge driver signal for UCC28950

Other Parts Discussed in Thread: UCC28950, UCC28070

Dear All,

I have problem with my DC-DC SMPS. I am using UCC28950 with i-coupler (ADUM1100) and drivers ADP3630. Final design should be 400 V to 12 V/80 A. I have no trouble with my solution without any load. Signals are correct (app. 50 % duty for each signal), but with load UCC28950 starts to send this strange driving signals. On my scope I watch on output signals of UCC28950. This strange acting starts at condition when output duty cycle starts to fall from maximum. In this situation are one Hi side fet and one low side fet on opposite side getting hot.

Because I had troubles with limitation because of current I have CS pin connected to ground and I have also connected DCM connected to ground. 

With shrim:

Without shrim:

Picture description:

Channel 1: voltage on one side of bridge

Channel 2: voltage on COMP pin

Channel 3+4: voltage on secondary side fets

Digital inputs are

Ha, Hb: High side FETs driving signal from the UCC28950

La, Lb: Low side FETs driving signal from the UCC28950

Sa, Sb: Secondary side driving signal from the UCC28950

Thank you in advance for your answers

  • Can you please specify me any condition when it can start acting like in my example? I didn't found it in datasheet. My UCC28950 is more than year old, but I think that it cannot be a problem.

  • Hi Michal.

    Is it possible for you to post the schematic about control section including the feedback loop?

    This is to figure out the control method chosen (peak current mode or different).

    Best Regards


  • Dear Flavio,

    Thank you for you reply, it helped a lot. I had chosen peak current mode and I wanted to use different.

    Best regards

    Michal Sitta

  • Hi Michal,

    Looking scope picture, it seems you are facing with noise issues.

    When the controller start and reduce the power stage duty cycle is because it is entering into regulation, modulating the phase of the bridge.

    A couple of suggestions

    - For first time debugging, use diodes instead of power mosfet for output rectification.

    This will help you in moving away some problems; you will loose some efficiency here but you may concentrate on one area at time.

    - Don't run the controller with CS pin shorted; increase filter capacitor on this pin instead.

    - When probing COMP pin, remember to put a series resistance between scope tip and pin itself.

    You can find more information on device data sheet for this (I personally verified this situation on my 3KW PSU).

    - Is your unit routed on a 4 layer board? Separate ground plane (control and power) are very important for noise immunity.

    - Are you using a current transformer for bridge current sensing?

    Be carefull on Ta reset when working at full duty cycle.

    All for now, please keep me posted with results

    Good luck!

  • Hi, Flavio,

    Thank you for your suggestions

    - Now I run CS normally without problems

    -I use serial resistor with probe on COMP according to datasheet

    - I use only 2 layer board with UCC28950 on same board as power parts

    - I am using current transformer 

    There are new scope pictures with DCM mode

    Now I have troubles with ringing without any load  

    Input voltage 170 V Output 3 V / 22 A

    Input voltage 150 V Output 3 V / 0 A - input power about 10 W (with larger input voltage become unstable)

    Input voltage 150 V Output 3 V / 0 A (100 nF/500 V X7R near primary mosfet) - input power about 10 W  (increasing with input voltage)

    I don't have lot of expediencies with ZVS, so I am not sure if adding capacitance near High side mosfets (behind current transformer) is good solution or it make thing worse. It helped with overshoots but I dint enough time for complete check.

    I have also troubles with ringing on secondary side it source is without load. I am already using RC + Diode for reduction of over shoots and dinging.

    I am able to adjust output voltage by changing reference voltage so I have change to test different condition. Source is working correctly with output 1 V and input up to 200 V (I didn't test more) UCC28950 normally run in burst mode and consumption is minimal

  • Is it good solution to add magnetic pearls on primary side mosfet drain leg for reduction of ringing or not? 

    Thank you in advance


  • Hi Michal

    Good to hear that some issues are gone away.

    Latest pictures posted show a real life situation.

    It seems you are using a series inductance with main transformer to help ZVS operation.

    Is this the case?

    Ringing on secondary side rectifier devices is due to this inductance.

    You can reduce ringing by placing a snubber network across each device.

    In case you are already using this, try and increase the size of the series capacitor.

    This will have some impact on overall efficiency but will be benefical.

    I don't think ferrite beads will help here.

    Please don't add any capacitance after the current sense transformer; place them before it.

    Can you run the power supply with some load on its output?

    If so, may you post a scope picture showing primary current on main transformer?

    You mention that increasing input voltage the unit becomes unstable.

    Try to add more slope compensation on current ramp signal lowering resistor value connected from pin RSUM (11) to GND.

    Have a nice day


  • Dear Flavio,

    I am using ADUM1100+floating drivers ADP3630 in my design and only 2 layer PCB (in next design I will probably use ADuM3221). I know that it cam cause trouble, but I am trying. Do you suggest to use impulse transformer?

    I didn't have lot of time for this project in last month. Today I tried something and this is result. I have great trouble with interferences during or near burst mode.

    It doesn't depend on input or output voltage or load  or frequency, but it depends on duty cycle. I disconnected secondary FETs in this test. For now I am using my "home-made" transformer with high leakage inductance. 

  • Happy new year Michal.

    Approaching or running burst mode means the converter is no more working with ZVS.

    Power mosfets are commutating in hard fashion so more noise is generated at each cycle.

    There's the chance that your high speed isolators are catching some spikes as trigger signal generating wrong driving condition.

    You can check this probing OUT vs driving signal to the mosfet (what about series gate resistance value)?

    Before changing the driving method, please check the threshold you set for continuos/burst mode (DCM pin) and see if it's possible to lower it keeping the converter in continuos mode.

    Than try and increase the size of the filter capacitor on CS signal (pin 15); this should attenuate the spike present at each turn-on.

    All for now; enjoy the circuit!


  • Dear Flavio,

    Thank you for your answer.

    Gate resistor is now 10 R (almost no change versus 3R9).

    I did few more tests and there are some outputs.

    I have new electronic load (Chroma 6314A +300 W output module 80V/60A) so I have more easier testing.

    With input voltage 150 V and output 2 V/ 25 A is efficiency only 75 %. To find out that is happening (where are largest losses) and I use only small heat-sink with parameter 22K/W  on my fets in TO220. According to temperature of heatsink I have largest losses on one mosfet (output B from UCC28950) that have temperature about 70°C (2W) (another 3 have temperature about 50°C (1 W). Do you think that it can be problem?

    There is picture from my scope (channel 3 and 4 are voltages on secondary side mosfets and channel 1 is current over transformer (shunt 0,1 Ohm). According to this picture current isn't same as I expected. Can you please look on it and send me some advice ? Is there problem with my transformer design (core ETD59 material N97, 42 primary turns, 2x2 secondary turns, )?

    Current floating throw transformer is really high or not?

    Thank you in advance


  • Hi Mike

    Mosfet's temperature should be roughly uniform; please check the drive signal on the hottest one.

    Voltage waveform on secondary side mosfet is OK; 7.5V from scope's picture that reflected on primary gives 150V.

    I agree with your doubt about current waveform; peak values don't match with load specified (25A).

    You mentioned about a 0R1 shunt for current measure: where did you place it in the circuit?

    Is the current waveform posted taken across this shunt resistor?

    From scope picture, converter frequency is about 250KHz up to now.

    Why not running at 100KHz for these tests? There's enough margin in transformer's design for this.

    Lowering converter's frequency will increase overall efficiency due to lower switching losses.

    In first notes exchanged, I remember that target voltage of this converter is 12V.

    May you try and increase input voltage and operating duty cycle towards the target values.

    You will see a significant improve in overall efficiency as well.

    Please let me know about results.


  • Dear Flavio,

    I was running at 200 kHz because this source was design for 200 kHz. Now I am trying to run at 100 kHz.

    There is large difference in running with disconnected output (0 A output current, same input voltage, frequency, output voltage) with enabled or disabled output E and F (secondary side rectifiers).

    Picture with enabled E and F:

    Picture with disabled E and F:

    As you can see, with disabled E and F channel UCC28950 is in burst mode, but with connected E nad F there is 2 times larger duty cycle => lower efficiency.

    I can not use disabling of E and F channel automatically because I need to use it with different voltage levels and with 2 V/10 A it is 10 V/2 A it is same because enabling is only according to power not according to output current.

    I did another test with one channel enabled and second disabled:

    As you can see there is non zero voltage on secondary fets during their on state that decrease efficiency and makes my primary fets more hot.

    I don't know what can be wrong, because it is problem of secondary side. 

    Btw.: current is measured across 0,1R / 2W, but it is not designed for this high frequencies and it is not hot => it is incorrect measurement probably because of self inductance. I need to find out some different shunt.

  • Hi MIke

    Pictures posted are fine.

    I mean syncronous rect. waveforms versus non syncronous are OK.

    Keep on with sync rectification; you need it in your application considering the range you wish to obtain from your converter (2 to 12V if I well understood).

    Stepping to diodes will heavily affects overall efficiency. 

    Behaviour with half sync rectification is correct as well.

    Let's work now on current signal. From latest pictures, it seems you are using a current transformer who is not capable in sustaining circulating current or operating frequency.

    This behavior is better visible now that working frequency has been lowered down to100KHz.

    We should expect a quasi square wave instead of a derivate one.

    In other words, using a 500KHz rated current transformer at 100KHz with robust circulating current can results in Ta core saturation.

    Please may you post more information about this area (type of Ta used and current sense schematic, if possible).

    A possible solution could be in using a Ta with higher turns ratio.

    In other words, suppose you are using now a 1 to 20, please go to 1 to 100 minimum.

    All for now; have a nice day.

  • Dear Flavio,

    Test conditions are now input 180 V , output 2 V/40 A => about 10 % output power with frequency 100 kHz. Same fate is getting really hot. As you sad I connected scope to gate of primary fets and there are results.

    Channel description:

    1/ voltage on the transformer

    2/ voltage on CS (33 ohms resistor and 1:100 current transformer) => current seems to be to high and it is strange that there is no current consumption during opening of hot fet

    3/ gate voltage of hot primary fet (low side)

    4/ gate voltage on second primary fet (low side)

    Last picture makes more sense, channel 2 is measuring current on input (shunt resistor 1 ohm on ground from the source). According to picture fet is hot because of floating current throw it. I also noticed that positive duty cycle is larger, I have to check what is wrong.

  • Dear Flavio,

    I particularly found the answer on my problem. Everything works great till my source starts to decrease duty cycle, it do it non-symmetrical.

    Now, I know why is my fet hot, but I don't know how to fix it. Do you think that I have problem in my feedback? I really don't know what can have influence on this behaviour. 

  • Hi Mike,

    Good to see that problems are going away

    Two advises: try and increase the slope compensation ramp signal lowering the value of resistor connected on pin 11.

    If the above does not cure the problem please check the feedback loop. As first trial, decrease the gain of the E/A and roll down to 0db earlier.

    Have a nice week end


  • Dear Flavio,

    Slope compensation didn't work, but change in feedback have large influence on this behaviour. I was able to change it to get same current consumption, but now I have to find best setting.

    Thank you for your great help in this project

  • OK Mike,

    Drop me a line in case of any needs



  • Hi Flavio,

    Now I finished 200 kHz 1,7 kW PFC with UCC28070 without any problems, but this DC-DC is killing me.

    I still have trouble with correct setting of feedback. Is there any chance that my problem is caused by stability?

    According to COMP is output stable, but duty cycle is not symmetrical (according to voltage over primary side transformer and also according to output A, B, C, D).

    Another problem is that I measure current by shunt (0,1 R) and on output of current transformer and they dont look the same.

    Here are some screens:

    yellow Channel 1: primary transformer voltage, blue channel 2 is current from shunt, green channel 4 is voltage on RCS before filter.

    Thank you for your help.


  • Dear Flavio,

    There is visible instability of my solution and something that I don't understand. I have same duty cycle (second picture), but current is changing/rising with visible delay and this cause this instability or it is caused by instability??? Strange thing is that now there is no current difference (as in "stable" COMP in previous post) in positive and negative half period.

  • Hi Mike

    Sorry for late answering to your posts.

    A couple of questions for you.

    In the first picture, first post, you shown current signal coming out from Ta.

    Is this the signal available on resistor after rectification?

    If so, you are probably facing withh Ta core saturation at high duty cycle.

    Please check that current signal going into the controller reach zero voltage at the end of each switching cycle.

    If this doesn't happen, probably the value of filter capacitor placed is too high.

    Picture posted here above shows a significant voltage drop on power switch during ON time.

    Look at yellow trace in the zoomed picture: during ON time, voltage on transformer has a negative slope while it should be flat.

    There's another possibility but I'm reluctant on this: check your scope probe frequency compensation :)

    Looking only at this latest picture, seems that a stability problem affects the PSU.

    Let's work on current signal before and than we'll jump on stability.

    Latest question: are you prepared to share the schematic about the controller section and feedback loop?

    This will help me in future analysis.

    All for now, go ahead with this!


  • Dear Flavio,

    I am glad that you are helping me with my problems. I am learning a lot.

    There is another screen, I checked my probe and it is perfectly compensated so problem is in my design. Purple colour is on Rs and green is after 1 kohm and 330pF filter. It doest  helped a lot to reduce 1 kohm to 220 ohm.

    Thank you in advance for your answer.

  • Hi Mike.

    Great! You are almost done.

    Looking at current waveforms there's last aspect to trim.

    Have you noticed that current waveform is one cycle little higher than the following one and so on (high, low than high again and low).

    Please add some more slope compensation and this sub-harmonic oscillation will disappear.

    Have a nice week end


  • Hi Flavio,

    I finish testing of changing of Rsum from 15 kohms to 220 kohms and i didnt found large difference.

    In attachment are pictures with same conditions (input 200 kHz, 90 V/1 A , output 35 A, app. 2,3 V) only difference if for first one 15 kohms and for second 220 kohms.

    Last picture is for same condition but frequency only 100 kHz (and there is most visible subharmonic)

    I dont know why, but green channel doesnt reach zero.


  • Dear Flavio,

    I also noticed that something really bad is happening during start. I connect small input voltage 20 V with loaded output (electronic load in CC and 30 A).

    It is not really good visible on single screen, but during this start are driving signal for FETs incorrect.

    Thank you in advance for your answer Flavio

  • Hi Mike.

    Please go in the opposite direction with slope compensation.

    Go down from 15K to perhaps 12 or 10K.

    Please remember that slope compensation setting is frequency related so you will have different results working at 100KHz and than going up at 200.

    Yes, you are right. There's something to investigate in sync fet driving signal.

    This is visible in previous picture, looking at green trace.

    There's a current spike visible on sync fet current trace who shows up alternatively.

    Please have a look on mosfet gate - source voltage instead of PWM output.

    Series gate resistor may play a significant role.



  • Dear Flavio,

    I went from 220 kohm to 15 kohm (but I already tested 10 kohms) with no change).

    As a primary side gate resistor I am using 10 ohm, it is lot, but it work fine without oscillations.


  • This is my scheme, maybe you fill find some error.

  • Hi Mike.

    Thanks for the schematic.

    I realized now you are using voltage mode control instead of current mode.

    In this case waveform posted and your comments are fine: there's no benefit in lowering Rsum due to voltage mode control.

    About current spike present on secondary current waveform, please check the correct timing between primary mosfet and secondary ones.

    Waveforms should be checked directly  across gate and source instead of PWM outputs.

    This will take into account for all propagation delays in each path.

    I have some doubts about the delay introduced with the NAND gates; why not using controller's capability?

    I was also impressed by the low value about output inductance: a large amount of ripple current to be filtered by output caps :)

    Have a nice day


  • Dear Flavio,

    Value of inductance was calculated based to frequency 200 kHz, but I am already using 6,1 uH.

    NAND gates are used because of propagation delay in primary side that is about 10 - 20 ns and it is caused by ADUM isolaters. I reduce delay by disconnecting capacitors.

    It is not possible to phase shift of channel E and F, it is only turn off delay, but I am facing that secondary fets are already tun on, but primary side it still off.

    Yesterday I found great problem with my PCB and it is too sensitive (secondary fets) to interferences that cause that fets are not correctly turning off and on.

    It is caused that this PCB is already almost year old. Now I will try to reduce sensitivity but it is sure that I will need to do upgrade PCB.

    Thank you Flavio for your help

  • Dear Flavio,

    I started new topic at and I would be happy if you will find time to look at it.

    Thank you in advnace

    Best regards