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A colleague of mine has seen similar.
I believe what may be tripping you up is the Rdmx resistor.
Duty cycle max is 92% minimum
Calculate and set Rdmx per eq 4 to set RDMAX at 140Kohm if Rt is 165Kohm (EQ4)
CDR to 6V - OK
222ns pulse - OK (200 to 250ns recommended),
3.3V levels on pWM are OK
100KHz to achieve 50Khz - OK
Rt =165k for FPWM = 45.5 KHz or so and is slower than sync input
Duty cycle max is 92% min
Calculate and set Rdmax per eq 4 to set RDMAX at 140Kohm
One hurdle down then. I did misread the datasheet in that Duty mx (min) is not an absolute number, but a tolerance +-3% around 95%. I am checking on how the clcoking works internally. I do know that the EVM and design sheets I have looked at have set it as high as 97%.