TPS65023 INT Output Timing

The INT output is a power good for all enabled DCDCs and LDOs except VRTC. Thus, if a rail is enabled but, is not within regulation the INT pin will be LOW. If you want to enable  DCDC1, 2, and 3 all spaced out in time of enable, there is a case where maybe DCDC2 and DCDC3 might be enabled and regulated but, DCDC1 is not enabled yet. In this case the INT pin will be high Z. But, once the DCDC1 gets enabled INT will drop to LOW again and after DCDC1 comes up, INT goes high Z again. Thus, the INT can go from LOW to HIGH and HIGH to LOW a couple of times before the power sequencing is done. 

This is where RESPWRON comes in handy. RESPWRON is asserted LOW when VRTC drops below 2.4V or when initial power up is occurring until VRTC reaches 2.52V. It is held LOW until VRTC rises again and adds a delay of the time set by TREPWRON. 

You can short the pins together. But if INT is pulled LOW by some deregulation of an output rail, it will not have any delay time required for going HIGH again. It will assert LOW and as soon as the rail is within regulation again the INT-RESPWRON will go HIGH. In order to get the delay time you must have RESPWRON go assert LOW and shorting INT to RESPWRON to pull RESPWRON to GND will not affect the function of RESPWRON because RESPWRON is an output and will remain high Z while INT is LOW, (unless VRTC drops below 2.4V). 

You can try asserting HOT_RESET LOW to assert RESPWRON LOW. This will not change any of the functions or I2C registers of the PMU other than, the DCDC1 Vout setting. It will be reset to the default voltage set by DEFDCDC1. 

Michael,

Allow me to provide some additional details about the design.

1: All of the DCDC converters and LDOs contained with the TPS65023 are being used.

2: The power-on sequence is DCDC1 (1.2V), DCDC3 (1.8V), followed by DCDC2 (+3.3V) and all the LDOs.

3: I have selected a timing capacitor which causes RESPWRON to remain asserted for a minimum of 300ms once VRTC becomes stable.

4: VRTC is used to pull-up the I2C bus termination resistors.

5: The HOT_RESET input of the TPS65023 is used in hand held applications to "wake up" the unit via a trigger device.

6: The RESPWRON output is pulled high via a resistor to the +3.3V output of the DCDC2 converter.

The capability I am trying to add is the predictable reset of the DSP in the event any power rails falls out of regulation. Ideally the TPS65023 would have some internal register settings which would allow the assertion of the RESPWRON output in addition to the INT output should any regulator fall 10% below its' target setting. However this part does not proivde that capability. This is why I am considering wire-or'ing the RESPWRON and INT outputs. I realize that an out of regulation condition will only result in the assertion of the INT output and that the assertion time will not be as long as that I have selected for the RESPWRON.

The piece of data I was trying to get information on was the mimum duration one might expect for the assertion of the INT output for an under-regulation condition. As I stated in my original enquiry the OMAP-L138 DSP requires a minimum pulse width of 100ns on its' reset input.

I disagree that wiring the INT output to the HOT_RESET input will work because there is a 30ms de-bouncing filter on the HOT_RESET pin. Therefore the INT signal would need to remain low for more than 30ms regardless of the duraiton of the out of regulation event in order to reliably invoke the assertion of the RESPWRON ouput. Am I missing someting here?

Michael,

Thanks for the response. It is sort of what I was expecting but I was just hoping that there might be some undocumented data which would ensure that the INT output met my 100nS minimum equirement. I would only sonsider adding a capacitor if I also added a buffer with some hysteresis to square-up the signal. The issue with the capacitor alone is that some parts attached to the reset line have a 5ns 10%-90% transition requirement.

I do not know if this forum is a way to provide feedback to the marketing and design teams but having the abiity to allow an under voltage condition trigger the RESPWRON output would b very valuable. This could be selectable via a register. Also, in this (PMIC) class of devices adding in a watchdog timer controllable via the I2C port and maybe a single dedicated pin to re-start the timer would also make this a more complete part. The RESPWRON would also be asserted if the watchdog timer expired.

David, 

There is the 5% hysteresis for INT thus, there will be a delay for the LOW to HIGH state transition of the INT pin. The delay time is just determined by the application and what is allowed onto the system.