Reducing noise interference between multple switcher

Hello Jacques,

That actually a great question and I'm sorry no one has replied yet. It's sort of a deep subject without a concrete answer but I can at least provide some guidelines of where to look and start.

Basically when using multiple switchers there can be beat frequencies between the switching frequencies that end up in the audio range and contaminate the analog domain. This electrical interference is usually conducted via the ground and Vcc(analog) power buses into the analog stages, but can also be magnetically coupled into a susceptible trace or device in the analog section or thirdly can be electrostatically coupled from the supply switch nodes into the analog path. When faced with electrically induced audible noise due to multiple supplies it is difficult where to place the blame because of the multiple mechanisms that might cause it.

All things being equal, the first step to avoid the interference might be to synchronize the switching frequencies of each individual switcher to the same clock rate. You'll have to access how affordable this is in relation to the added cost to the product depending on the synchronization method used. Also the design may have a mix of device types that are sized for different current levels and may not all have provisions for synchronization or have dissimilar switching frequencies. Clocking circuits for synchronization circuits usually don't require crystal oscillator precision, though there is no harm in using a crystal. There may be an available uP clock that can borrowed for the function or you might find an IC timing function that is low in cost to use. (I think 555 timers would be too imprecise to apply.)    There is also benefit to staggering the phase of multiple switchers in that input current ripple reduction may benefit the system and reduce input capacitor ripple current requirements. My favorite device for multiple phase clocking is the CD4017B. It's roughly 40 years old but TI still makes them. It is a decoded divide by 10 counter with outputs numbered 0 to 9. If you need a three phase clock tie output number to the reset input and use outputs 0, 1 and 2 to clock the three switchers. You could get up to 10 phases with a single IC. Also there may be a spare uP timer output that could serve as a signal source for the x3 main clock input of the CD4017B. There are many ways to configure the clocking tree and generally synchronization need not happen during the power-up and soft-start periods. I recommend that you bench test the chosen approach fully before committing to PCB because of several pitfalls that can arise> To wit:

There are a few switchers that have very wide synchronization frequency capture ranges to the degree that if they are presented with a constant logic high on the sync input they treat this a "zero hertz" and stop switching. This flaw can be side stepped by AC coupling (with a series capapitor) and dc restoring (with a diode or two) the input clock to prevent it ever staying at logic one during power up or fault periods.

The next problem is that some micropower switchers drop into PFM mode (no longer constant frequency) when operated at light load. When driven from a frequency synchronization source  they might not operate in the low power PFM mode properly and system power conversion efficiency will be reduced.

As an alternative to synchronization there may be a combination of LC (small L - say <1.0 uH) input and / or output filters that could be aaded to each switcher. It's difficult to predict these values ahead of time but there are some Murata (LQH3Cxx and simlar numbers) that are small wound bobbins that can be replaced by a zero ohm 1210 resistor if not needed. It is important to plan ahead and have a "home" for LC filters to live so they can be evaluated as to whether they will be beneficial on not. If you try using ferrite beads remember that many of them may have a 1 amp rating but in fact lose effecivness due to saturation above 100mA so find the correct data sheets when selecting for this type of application. The LC (or in low current cases RC) approach to interference reduction should be used to address conducted type of interference.

Electromagnetically coupled interference can possibly be tracked down using a small loop antenna tied to a coax cable and nd connected to a scope input or audio amplifier and speaker. This king of interference can get coupled into small signal transformers or circuit loops. Using shielded inductors in the power supplies can also help. But we know of instances where inductors exhibit a polarity. (one mounting configuration causes interference and the other direction does not.) Interestingly, these inductors often have a dot marking over one terminal.

Eectrostatically coupled interference can only be resolved with proper PCB placement between the switchers and the prone analog section. Shielding that is tied to ground might assist here.

 There is also a forum entry that I wrote a few months ago on a method of reducing switching spikes on the output of SMPSs. You can search for entries under my name. If you can't find it let me know and I'll dig up the link.

Hope this sheds some light.

BTW We can also be reached at SimpleSwitcherApps@TI.COM

Alan Martin

BTW: I must also clarify that the term synchronous in "synchronous switching regulator" refers to synchronous rectification and not to the fact that the device may or may not be capable of having its switching frequency controlled by an external clock.