BQ24450

Let me ask another question.

As far I understand, the external pass transistor will run in the active mode ( not as a switch ). I am wrong?

Assuming that I want charge a battery 12V / 7Ah and the supply voltage will operate between 20V-30V, and the configuration of bq24450 shall be with pre-charge and a Dext device, the topologie used is the NPN Emitter Follower.

Design example

The results were as follows:

Is it ok ?

Regards

Correct, the BQ24450 is a linear charger.  Your chosen transistor looks acceptable, but keep in mind your operating conditions.  How long/often will you run at 30V in?  At 750 mA charge current, that is over 10W lost in the transistor.  You might look into stepping your input voltage down with a switcher, such as the TPS5410.

By my calculations, I get Rd=422k.  The other values looked correct.

Hello again,

Yes, Rd=422K ; I got it, but I defined  1% range around it, so the values were 417K and 426K and I picked 412K. My mistake.

How do you get Pd = 10W; the formulat in datasheet is confused

Using Vinmax = 30V; Vout = 14,4V ;hfe = 200;Imax charg = 750 mA and Rp = 1200 ohm ,

It hardly will run at 30Vin , but can happen.

I'll see the TPS 5410 in order to reduce Vin.

Pd is the power lost in the IC.  For the emitter follower topology, this power is equal to the drive current power minus the power lost in Rp.  The second term in the equation should read: (Ichg/ hFE)^2 * Rp.  Thus, it is simply an I^2R formula.

The power lost in the NPN transistor is the voltage across the transistor times the collector current.  This is equal to the charge current (max) * the max differential across the transistor, which is Vin (max) - Vout (min).  I suggest stepping the Vin voltage down.

Stepping Vin Voltage down using for instance TPS5420 and using the switcherPro Design the new output Voltage range is 18,186V - 17,175 V, which change the topology.

It´s not an issue, but in fact the initial NPN Emitter Follower will change to the another one Common Emiter PNP, as DV changed from 4,6 V to 1,8V.

Do you agree with it?

Yes, with the TPS5420's maximum duty cycle of 87%, the highest output voltage you can reliably achieve from a 20V input is 17.4V.  This gives 3V of headroom for the drop across the transistor and sense resistor, which should be just enough for your 14.4V output.  But a change of topology does give more headroom.

Can a MOSFET be used as the pass transistor to reduce loss? 

If so, do you have any suggested components/configurations?

A MOSFET would not significantly reduce the power lost in the system.  The main source of power loss is because the pass element (either BJT or FET) is being operated in the active region.

The output drive of the BQ24450 is single-ended.  It can only source or sink current but not both.  This is okay for BJTs, which are current driven devices, but is not okay for MOSFETs, which require charge to be added or removed from their gate.  For example, if the BQ24450 is setup in the NPN emitter follower topology and uses an NFET, then there is no way to pull down the gate and remove charge.  Possibly a resistor from DRVE to ground would provide the pull down, but that is extra loss.

TI now carries MOSFETs: http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=analog&familyId=1647&uiTemplateId=NODE_STRY_PGE_T

The Pd formula in the datasheet is *very* confusing...it would be nice if you would use parentheses to indicate order of operations. 

Can you reply with the Pd formula parenthesized (and yielding the same results as the application example on page 15 of the datasheet)? 

Per the example,

   Vinmax = 13v

   hfe=25

   Imax-chg=600mA

   Rd = 464000

How do you get 126mW from

    Pd=(Vinmax-0v7) / hfe * Imaxchg - (Imaxchg^2) / (hfe^2) * Rd

In general if you could post a reply with the corrected formulas and values from the datasheet example it would be very helpful.

Thank you!

Your reasoning to get Ra and Rb is correct, but this equation is a little off: 2.3 = (5.25 * Ra) / (Ra+Rb+(Rc||Rd)).  Ra in the numerator should be Rb + Rc||Rd to get the usual voltage divider form.  Thus, Rb would equal 16.9k and Ra would be 75k as noted earlier in this thread.

There is a typo in the Pd formula on page 15.  Rd should be Rp, as the formula correctly contains on page 14.  This gives 126 mW for Pd.  We are currently updating the datasheet for clarity, but in the meantime here is the correct formula for Pd for the circuit on page 15:

Pd = [(Vin(max) - 0.7V) * Imax-chg] / hFE - [(Imax-chg / hFE) ^ 2 * Rp]

Oops...thank you!

Using the David Albert´s example can anyone explain how to selec the external pass transistor ?

First, this is the corrected example, I goofed on one of the calculations, thanks to Chris for pointing that out.

My design parameters:
    Final discharge voltage (1.75v/cell) = 5.25v (Vth)
    Float voltage (2.25v/cell) = 6.75v (Vfloat) (2.25 instead of 2.30v/cell for longer life)
    Boost voltage (2.45v/cell) = 7.35v (Vboost)

Data sheet suggests an input bias current through Rd
of 50uA (see page 15) so:
    Rc = 2.3 / 50uA = 46K
    Closest 1% resistor is 46.4K

When charging is completed, a float voltage is applied (Vfloat)
to maintain the battery charge.  The desired float charge is
6.75v and is set when STAT1 (pin 10) turns off, removing resistor
Rd from the voltage divider so that the V_SENSE (Vfb) input
is determined by Vbat * (Rc) / (Ra+Rb+Rc).  The charger attempts
to drive VSense to Vref (2v3), so we want
    2.3   = (6.75 * Rc) / (Ra+Rb+Rc)
        (Ra+Rb) = 1.9347826*Rc
        (Ra+Rb) = 89774

When fast charging, pin 10 goes low which adds Rd to the
resistor divider. 
Note: Rc||Rd denotes the parallel value of Rc and Rd
    Vsense = Vbat * (Rc||Rd)  / (Ra+Rb+(Rc||Rd))
and the chip attempts to drive Vsense to 2v3  So we want
Rc||Rd to change the value of Rc such that Vbat is 7.35v.
Since Ra+Rb=89774 and Rc=46.4K we have:
        2v3 = 7v35 * (46.4K||Rd) / (89774+(46.4K||Rd))
  40891 = (46.4K || Rd)
        344408 = Rd
    Closest 1% resistor = 348K
    Note: then (Rc||Rd) = 40941K

Vth defines the threshold for turning on the fast charger
(external pass transistor) and should be above the battery
final discharge voltage to prevent outgassing due to fast
charging while the battery is severely depleted.  The desired
threshold is 5v25.  Vth is sensed at pin 12 (Chg_En or CE)
and when it is below Vref (2v3) prevents fast charging). 
The voltage at pin 12 when power is first applied is defined
by the resistor divider
    (Rb+(Rc||Rd)) / (Ra+Rb+(Rc||Rd))
Vth should be kept below 2v3 until Vbat climbs above 5v25
    Rc=46.4K and Ra+Rb=89774K and Rc||Rd=40941
    2.3 = (5.25 * Rb+(Rc||Rd)) / (Ra+Rb+(Rc||Rd))
    2.3 = (5.25 * (Rb+40941)) / (89774+40941)
    Rb = 16325
    Closest 1% resistor = 16.2K

Since Ra+Rb = 89774K and Rb=16.2K
        Ra = 73574
        Closest 1% resistor is 73.2K

So: Ra=73.2K, Rb=16.2K, Rc=46.4K, Rd=348K
    Vfloat = 6.74138v
    Vboost = 2.3 * 130715 / 40941 = 7.34336
    Vthreshold = 2.3 * 130715 / 57266 = 5.25

Hopefully I got it right this time...

Afonso, the pass transistor selection is made based on input voltage, peak charging current, and hfe.

For example:   Vcbo, Vceo = 80V, Icmax=3A, hfe min = 25 @ Ic=1A

The current through the pass transistor during bulk/boost charge is determined by Risns where 250mV/Risns = charge current

Chris, I couldn't find a TI part, but parts like a TIP32B or BD242B seem like a good fit and can dissipate a lot of heat with a proper sink.

What is your target bulk/fast-charge current and voltage?

Thanks David for your explanation.  I agree.

To elaborate: The key care abouts in the pass transistor are the voltage rating, power rating, and hFE (beta) value.  As shown earlier in this post, the transistor will get hot--it must be sized (physical size) to handle the power dissipated in it.  This power = [Imax-chg * (Vin(max) - Vout(min))] + [(Imax-chg / hFE) * 0.7V].  hFE should be large enough such that no more than 25mA is required for a base drive, as this is the limit of the bq24450's base driver.

The battery to be charged has the parameters as follows :

Vbat = 12 V

Cap. - 7Ah - Ifast= 0,7A;Ibulk= 0,07A;

External Supply

Calculated values based on BQ24450 Dsheet

Ra =205K ; Rb = 14K ; Rc = 46,4 K ; Rd = 422K

Risns = 330 mohm

I think that topologie shall be common emitter PNP ( do you agree?)

Based on it, if  Idrve = 25 mA, hfe min = I fast / 25mA -> hfe min = 700 / 25 = 28

what are the to follow in order to select the external device?

Using de BD242A for example.

Yes, common emitter PNP would be a good topology.  If you do use it, you should look into reducing the output of the TPS5420 to around 15V minimum, since the common emitter PNP topology requires less headroom.  This will increase the efficiency of the circuit.

You can begin by calculating the power lost in the PNP.  Then, you pick a transistor package that can handle that much power.  For this design, I would stick with a TO-220 package.  Then, find a transistor with a minimum beta greater than 28.  The BD242 has too low of a beta.  Fairchild's KSA614 should work, as should many others.

Chris,

If I´m understanding your idea, and reducing the output to around 15V min ( with TPS 5420 I got Vmin = 15,038V ; Vmax = 15,917 V), the DeltaV obtained is Vmin - Vboost = 15,038V - 14,4 V = 0,638V.

Including a blocking diode ( 1N5392 for instance ) with a Forward voltage of +- 1V, I get a negative  value, so I´ve to increase the 15V output of TPS5420 in order to get a higher voltage at the SLA Battery.

Am I wrong?

You are correct.  If a diode is included in series (as done in the figure 9 example), then the dropout of the common-emitter PNP solution is no longer 0.5V but is 0.5V + Vf of the diode.  You should scale up the output of the TPS5420 accordingly so that the output of the TPS5420 - (14.4V + 0.5V +Vf) is greater than zero.

I'm trying connect STAT1 and STAT2 pins to a processor in order to display the charging status.

Is there an example of how to do it ?

STAT1 and STAT2 are simply open drain/collector outputs.  Just connect each of them to your processor inputs with a pull up resistor.

Yes I understand it, but I´m using the dual-level with pre charge, meaning that STAT1 is connected to RD resistor.

Once I want to connect STAT1,STAT2 and PGOOD to controller, is there any unwanted effect when I pull up each  pin? It don't happen with STAT2 once is not connected .

The issue only can be with PGOOD and STAT1 ( I think).

Can this operation ( pull up pin 7 and 10 ), change the operating condition of bq24450?

We can analyze the circuit in figure 9 of the datasheet.  As you note, a pull-up on STAT2 is fine.  PGOOD already has a pull-up of value Ra+Rb+Rc.  If PGOOD is high-Z, then the IC has no power and all the outputs are floating.  So, PGOOD is already pulled up by the 3 resistors.  Likewise, if STAT2 is high-Z, then the IC is in float mode and Vfb has 2.3V on it.  Thus, STAT1 has a pull-up (Rd) on it that will pull it up to ~2.3V.  This should be high enough for most logic levels.

I think that you are refering the Hi-Z state of STAT1 in float mode.

If PGOOD is Hi-Z, the input voltage at Pin 7 should change between 0V to VslaBattery ( maximum).

So we must step down this voltage in order to enter it into a microcontroller ( max 5V ).

Yes, STAT1 in float mode.  Thank you for catching my error.

Yes, the pack voltage will appear on PGOOD (and STAT1) if there is no input voltage.  I believe you have a couple of options.  You could just add a zener diode to each of the pins that would clamp the voltage to an appropriate level and then tie the pin directly to your uC.  Or you could connect an NPN BJT's base or an N-MOSFET's gate to the pin and tie the collector or drain to your uC input with a pull-up resistor.

Hello,

I am using a 12V battery for a U.P.S. design that uses BQ24450 to monitor the battery. Have I selected the right resistors?

Parameters:

Vth=10.5V; Vfloat=13.8V; Vboost=14.7V; Vin=18V regulated; Ichmax=1A

Resistors and components, calculated:

Rc=46k

Risns=250milli

Rd=588k

Rb=17k

Ra=213k

Rt=100

Rp=600

pass transistor: 2SD882

blocking diode: 1N4101

2867.Calculator Final.xls

Please find the calculator I put together for this.

With your values, you will get the following actual voltages:

Vfloat 13.70086207 Volts

Vboost 14.60052193 Volts

Vthreshold 10.46414206 Volts

Oli,

Thank you for posting your calculator here!  It looks good.  If you enter the values from the datasheet design, then it returns the same results as the datasheet.  This is a good check that proves it works.

Chris,

Are my selections for resistors, external diode, and external transistor ok (see post up two posts)? Also, what does the BSTOP input do? Lastly, how do the signals PGOOD and STAT1 talk to a microcontroller if they are already connected to the external resistive voltage loop (I understand they are already pulled up to 2.3V, but my uP needs 4-5V logic high)?

Thank you for the help! I love BQ24450!

Dax

The post after yours contained an excel spreadsheet with the calculations for the resistors.  The datasheet also contains the equations for calculating them.  You can check the math yourself.

Digikey says that transistor will not be restocked once they deplete their current stock, so you may want to think about getting a different one.  Also, I am concerned that the NPN topology does not give enough headroom for your design.  The 2.7V required by the transistor plus the 250 mV drop across the sense resistor plus the drop across your diode will sum to more than the 3.3V of headroom in your current design (18-14.7) without even considering the likely tolerance on the 18V input.  Also, you don't want to use a zener diode for the blocking diode, but simply a standard silicon (not schottky) diode.  I believe others in this thread have listed what they are using.

As explained in the post before yours, to use PGOOD and STAT1 with a microcontroller and in the voltage divider, you need to make their signal level compatible with your processor.  Are you sure the logic high level on your processor is 4-5V?  That seems awfully high for a logic 1.  Even so, I think connecting an extra transistor's gate to each of the PGOOD and STAT1 pins would successfully translate the voltage on the pin to your processor's needed level.  You would tie the gate to the pin, source to ground, and drain to the processor input with a pull-up resistor to whatever voltage you want.

As noted on page 5 of the datasheet, BSTOP "Taking this pin from low to high transitions the charger from Boost Mode to Float Mode."

For PGOOD and STAT1 to interface with uP, if I tie the pins to the gate of an NPN or NMOS, then the VBE (or VGS) will be equal to Vbat(max) at some time. 12 V is too large for the absolute ratings on datasheets for max VBE. What should I do? I was thinking of Zener clamp, but then the added series resistor will mess up the resistive feedback network Ra-Rd.

For most BJTs, the rating is the emitter-base voltage rating.  This is the maximum voltage that can be applied from the emitter to the base.  This represents the reverse voltage on the P-N diode in the BJT.  Going from base to emitter, you have a P-N junction which is simply a diode drop.  Being a BJT, this will draw some current to drive the transistor on and this may affect the voltage divider.  A FET will not have this issue of current draw so I would recommend it for this circuit.

There are many transistors out there with sufficient (>12V) gate source ratings to work in this circuit.  We have some here: http://focus.ti.com/paramsearch/docs/parametricsearch.tsp?family=analog&familyId=1941&uiTemplateId=NODE_STRY_PGE_T