• State Resolved
  • Locked Locked
  • Replies 1 reply
  • Subscribers 63 subscribers
  • Views 376 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

LM3881 Incomplete Power-down Sequence.

Go
Genius 4220 points
Other Parts Discussed in Thread: LM3881

Hi,

I found the description about the behavior of the incomplete power-up sequence in LM3881 D/S Page9 figure11.

But I couldn't find the description about the case of incomplete power-down sequence.

(means If the EN pin turns to High before the Flag1-3 output become Low (in the case of INV pin is Low)

Regarding it,

I think the behavior will be like  the attached file, is it correct?

if correct, I'm not sure how many clock cycle is needed that the Flag2 or 3 become High after the EN pin turns to High,

8 cycle or 9cycle?(please see the attachet file)

Thanks

Go