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TL7700 hysteresis setting quirk

I'm using a TL7700CPSR, with R1=390k and R2=27k//100k (using the designators in Fig. 19 of the data sheet) to obtain thresholds of about 9V5 and 10V5. Ct is 100nF. 

I'm using a digitally controlled bench power supply to allow precise changes in the input voltage, and 100:1 probes on the scope. The input voltage is decreased from 10V55 to 9V55 in one step, and then in 10mV steps: 

Input voltage

/RESET pin state

Ct voltage

Current sink ("Is") state

Stability if input voltage is held constant

9V55

High

1V45

Off

Unstable. Ct voltage "spikes" to ~325mV about once per minute.

9V54

Low

327mV

Off

Stable

9V53

Low

322mV

Off

Stable

9V52

Low

64mV

Off

Unstable. Ct voltage "spikes" to ~325mV about once per minute. Current sink turns on after a while.

9V51

Low

58mV

On

Stable

As long as the Ct voltage is higher than the 58mV, I can take the /RESET pin high by changing the input voltage to 9V55 and low by changing the input voltage to any value between 9V52 and 9V54. I can change it high and low repeatedly. 

Only when I reduce the input voltage to 9V51 does the internal current sink turn on, as can be seen by a ~50mV step in the SENSE pin voltage. After this happens, the /RESET pin only goes high after the input voltage increases to 10V49, as it should be. 

Looking at the block diagram in the data sheet, it is unclear how the latch can be set without the current sink also being enabled, so I guess it lies in the detail of the implementation. Is there a workaround for this behaviour?

Thank you! Heinrich