12V to +/-100V by using TPS40120 with flyback topology

Hi Sheng-wei,

First to answer your questions.

1. The turns ratio is typically selected to set the operating duty cycle. Most designs try to keep the duty cycle below 0.5 to limit stress on the secondary side components. Assuming you're operating in CCM, the duty cycle with a 1:10 transformer is calculated by D = (VOUTxN)/(VIN+VOUT*N) = (100*0.1)/(12+100*0.1) = 0.45. With a 1:20 transformer it is 0.294. Based on this I expect either turns ratio to work.
2. I have never used TINA before to estimate efficiency but in this case I think it is different because there is some other factor in the real circuit not accounted for in the TINA simulation.

I'd like to take a look at a few things to help figure out the issue here. I do not see anything clearly wrong right away. I do recommend some more margin on the breakdown voltage rating if the schottky diode. 100V for a 100V output gives no margin. Additionally the input voltage is reflected from the primary winding to the output winding.

1. What is the output current or total output power designed for?
2. Schematic of the tested circuit on the EVM. Is this the same as the TINA circuit?
3. TINA .tsc file used for simulation so I can also test. It looks like with the 1:10 transformer the device stops switching normally.
4. Any calculations used to select the components in the design
5. Screenshots with a smaller time scale which clearly show the individual pulses on the switching node and the gate drive signals

Thanks in advance for this information.

Best Regards,
Anthony

Hi Anthony,

Thanks for the reply. About your questions :

1. What is the output current or total output power designed for?
   >> 0.1A on both +100V and -100V 
2. Schematic of the tested circuit on the EVM. Is this the same as the TINA circuit?
   >> yes, all are the same component and values, except the transformer, they do not provide a SPICE model for transformer so I use an ideal model instead
3. TINA .tsc file used for simulation so I can also test. It looks like with the 1:10 transformer the device stops switching normally.
   >> the TINA .tsc file is already attached in my first message : 5621.TPS40210_100V_flyback.TSC 
   >> No, TPS40210 does not stops switching, but the duty cycle reaches about 100% while the output voltage does not go higher anymore, see below figure
    
4. Any calculations used to select the components in the design
   >> not too much calculation. Just adjust output voltage to +100V(R5 = 360 Ohm), switching frequency at 600kHz(C3/R6), ignore over current protection(R11 = 0), and soft-start time about 50ms(C5=1uF)
5. Screenshots with a smaller time scale which clearly show the individual pulses on the switching node and the gate drive signals
   >> as the answer on question 3

Also, I had used a 400V diode to run the simulation before, but the result is the same, so I changed back to Vishay SS210 to as this is the part on my hand.

Really appreciate for your help !

Sheng-wei

Hi Sheng-wei,

I'm planning to look a bit closer at this later. Thank you for pointing me to your first post for the tsc circuit. I overlooked this the first time. We might need a better model for the transformer in order to simulate this properly as a flyback. I'm not seeing anywhere to input the primary inductance of the transformer.

Another quick comment is I recommend not testing with a 0 ohm resistor for current sense resistor. I would select a value to set the peak current limit of the device instead. I will need to do some calculations to figure out what this limit should be and to come up with an equation to calculate this. It will depend on if the design is operating in CCM or DCM.

Lastly for the screenshot, can you please also show this with the circuit you have built up? Thanks in advance.

Best Regards,
Anthony

Hi Anthony,

Another quick comment is I recommend not testing with a 0 ohm resistor for current sense resistor. I would select a value to set the peak current limit of the device instead. I will need to do some calculations to figure out what this limit should be and to come up with an equation to calculate this. It will depend on if the design is operating in CCM or DCM.

>> In real circuit test, we also found if we keep 10m Ohm on ISNS pin(which means 15A over current protection), output voltage can only reaches +/-30V for a few seconds(with any load), then goes into over current protection. So we decided just neglect over current protection for now to keep on our tests.

Lastly for the screenshot, can you please also show this with the circuit you have built up? Thanks in advance.

>> here are two example : (yellow : GDRV / blue : 12V input current, 1V = 1A)

Case 1, +/-30V output without load

input power : 12 V X 0.158A = 1.896W
output power : P = 0W
effieciency = (Vout/Vin )x100%=(0W)/(1.896W) x100% = 0%

Case 2, +/-30V output with 4kOhm load on both +30V and -30V

input power : 12 V X 0.245A = 2.94W
output power : P=(30.298)²/4000=0.2295W
efficiency : =(Vout/Vin )x100%=(0.2295W)/(2.94W) x100%=7.805% 

As you can see, GDRV does not reaches to 100% duty cycle which is pretty different from TINA simulation, I have no idea why they are so different.

Thanks for the help again.

Sheng-wei

Hi Sheng-wei,

I would not trust the TINA simulation. A better model for the transformer is needed for this simulation. With no load the duty cycle should be very low. With full 100mA load on both the + and - outputs the duty cycle will be around 50%.

The design may be restarting due to instability and not over current protection. I now noticed in the TINA schematic the Cc and C4 values or opposite of the typical compensation network. Cc is typically in the nF range while C4 is smaller. I recommend trying Rc = 30kΩ, Cc = 100nF and C4 = 1nF. I have selected C4 to cancel out the ESR zero of the output capacitors. With the amount of output capacitance this design has and the equivalent load resistance I think the 30kΩ Rc will set the gain of the compensation low enough so there will be more than enough phase margin. If not please try Rc = 10kΩ, Cc = 270nF, and C4 = 2.7nF next.

Also please keep the 10mΩ current sense resistor. This is small enough so the internal slope compensation is sufficient and will provide high enough current limit. The current sense resistor is needed to sense the current waveform in the switch for the internal PWM control circuitry.

Lastly I noticed there is an extra capacitor from the gate of the FET to ground. Can you remove this? I also recommend adding a series gate resistor to the FET. A value in the range of 5-20Ω.

If none of this works you could also try reducing the switching frequency to 200kHz to see if it has any impact as well. 600kHz is higher than most flyback designs. I'm also not sure how clean the layout can be when using a TO220 FET on a board not made for it. Layout is critical for switching regulators.

Best Regards,
Anthony