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TPS40210 configured as isolated forward

mod13192
Prodigy 90 points
Other Parts Discussed in Thread: TPS40210, TL431

Hi,

I want to use TPS40210 as an isolated forward converter. (I want to minimise o/p ripple)

Can i configure it this way? How would the feedback be?

My requirement is 9 to 36V input; output is 5.1V 1.4A

Thanks.

  • 0
    TI__Intellectual 1955 points

    Hi Mod,

    The TPS40210 can be operated as an isolated forward converter, however the internal error amplifier will make the feedback process a little tricky. 

    Typically in an isolated design customers use a TL431 shunt regualtor and opt-coupler to pass outvoltage and frequency compensation across the isolation barrier. 

    Page 10 of the Third Quarter 2008 edition of TI's Analog Applications Journal (http://focus.ti.com/lit/an/slyt297/slyt297.pdf) shows the schematic for the TPS40210 in an isolated flyback configuration, but the isolated feedback scheme is the same.

    The TL431 on the secondary side performs the reference comparison and loop compensation.  An opt--coupler passes the resulting control information across the isolation barrier and the TPS40210's error amplfiier drives the control voltage (COMP) to generate the required PWM signals.

    Regards,

    Nancy

  • 0 in reply to nancy!
    Prodigy 90 points

    Thanks Nancy...

    I already did it on my PCB layout... waiting for the sample IC to arrive

    I still have some questions.

    What is the practical reset ckt for the transformer? (I implimented RCD on my layout but consumes a lot of space). Is a resonant reset applicable?

    If i will not add a reset ckt,  it probably not destroy the MOSFET switch (i will use 100V) but will the transformer saturate? Switching frequency is 400KHz.

    What is the maximum allowable duty cycle at the lowest input voltage?

    Regards,

    mod

  • 0 in reply to mod13192
    TI__Guru 56825 points

    I already did it on my PCB layout... waiting for the sample IC to arrive

    I still have some questions.

    What is the practical reset ckt for the transformer? (I implimented RCD on my layout but consumes a lot of space). Is a resonant reset applicable?

    RCD will offer several advantages for reset.  It is more efficient than rosonant reset, produces cleaner waveforms and allows higher duty cycles.  Resonant reset has lower efficient, applies more voltage stress to the switching FET (typically upto 2x the input voltage) and can have issue above 50% duty cycle.

    If i will not add a reset ckt,  it probably not destroy the MOSFET switch (i will use 100V) but will the transformer saturate? Switching frequency is 400KHz.

    If the duty cycle doesn't exceed 50% you shouldn't have a problem with saturation using resonant reset.  At higher duty cycles resonant reset can have reset issues with the transform's V-s becoming unbalanced.  Without a synchronization circuit, there is no effective way to limit the maximum duty cycle of the TPS40210

    What is the maximum allowable duty cycle at the lowest input voltage?

    For the IC's limitation, at low-line, the controller can operate upto 95% duty cycle, however this would likely damage a forward converter with transformer saturation.  In practical terms, you should adjust the transformer turns ratio to make sure the converter is always less than 50% duty cycle to provide for transformer reset. 

    The only way to effectively Duty Cycle Clamp the TPS40210 is to pull the RC pin above Vin / 20 during the unused portion of the duty cycle.  (Applying a 60% duty cycle pull-up on the Vin pin via a diode pull-up effectively synchronizes the TPS40210 to the falling edge of the external signal and limits the duty cycle to 40% (1-D of the synchronization signal)

  • 0 in reply to mod13192
    Prodigy 90 points

    Hi Peter,

    Thanks for the clarifications.

    Unfortunately, samples ICs will not be available 'til next month.

    For the mean time, could you send the link for simulation software using a/m IC configured as forward converter. The one on your web is for boost.

    Thanks again and more power.

    Cheers!

  • 0 in reply to mod13192
    TI__Guru 56825 points

    Mod,

    There is no forward converter simulations tool currently available for the TPS40210 controllser.

  • 0 in reply to Peter James Miller
    Prodigy 90 points

    Hi Peter,

    I am now doing the initial test of TPS40210, evrything seems fine except for the UVLO trigger point.

    It starts operating at 4.7Vin (there is unbalanced V-S), when it reaches 5.4V the OCP kicks off making it re-start. At the time Vin is 6.1V the output is already regulated but the transfomer is not resetting properly. 

    Is there any way that i could adjust it to around 8V with hysteresis of 0.5V?

    Thanks.

  • 0 in reply to mod13192
    TI__Guru 56825 points

    The TPS40210 controller does not include a programmable UVLO function, so you'll need to build an external UVLO function using the IC's Disable Pin.

    The Disable Pin has an internal pull-down, so the pin must be externally pulled-up to be disabled.  Pulling this pin low will turn the IC on.  Unfortunately this isn't going to be a trival circuit and the design will depend on what other rails may be available in the circuit at the time.

    You can build a very "rough" (loose tolerance) UVLO with a resistor divider and an N-channel MOSFET.  A diode, resistor and capacitor from the gate driver can feed additional current into the divider to provide hysteresis.  For more accuracy, you'll have to go to a comparator to drive the N-channel MOSFET or the disable pin directly.  Again, a diode from the gate to a capacitor (peak detector) with a resistor to the junction point of the resistor divider for the UVLO sensing will provide hysteresis by providing additional current once the TPS40210 converter starts switching.

    NOTE: The BP regulator is disaled when the disable pin is pulled high (IC disabled) so this pin can not power the UVLO circuitry.

  • 0 in reply to Peter James Miller
    Prodigy 90 points

    Hi Peter,

    I just build a UVLO with a loose tolerance as u satated, but instead of adding a peak detector ckt from the gate driver i used the BP pin with a 680K resistor to the junction of the resistor divider.

    It works fine now.

    Your forum is a great help... keep it up

  • 0 in reply to mod13192
    TI__Guru 56825 points

    One caution on using the BP voltage for UVLO hysteresis.  The hysteresis on turn-off will be much lower as it takes a long time for the BP regulator voltage to discharge in shutdown.  To see if this could be a problem in your circuit, run the converter under full load and then provide the slowest Vin power down profile you expect.  The concern is that during power down when the converter reaches UVLO_off and load on the source is removed the input voltage will increase sufficiently to turn the converter back on.  Since BP has not discharged the hysteresis going from UVLO_OFF to UVLO_ON will be fairly low.

    Using the peak-detector improves the UVLO in this case by using a much smaller capacitor than the BP regulator to allow this voltage to discharge much more quickly.

  • 0 in reply to Peter James Miller
    Prodigy 90 points

    I will check it out when i get back to work on monday.  I also reduced the cap on BP pin from 1uF to 0.47uF

    One concern i have is the o/p line ripple when Vin is greater than 26V and load current is at minimum(50mA). The converter seems to reach its minimum duty cycle and it is cycle skipping ,creating a line ripple of about 50mVpp. I tried to play around the compensation values, and turns ratio of the transformer but may attempts failed. Though the ripple has a relatively low amplitude, it is to me an unstabilty of the power supply. Pls enlighten...

  • 0 in reply to mod13192
    TI__Guru 56825 points

    Mod,

    If you are operating below the minimum pulsewidth of the controller, the switching frequency will be less than that of the internal oscillator, which would force evaluating the stability of the converter at 1/2 or less of the switching frequency.  In addition, the change in switching frequency changes the loop characteristics of the modulator, drastically changing the total loop response which could be resulting in unstable operation.

    With only 50mV of output ripple, it is more likely that the ripple is a result of overshoot from a minimum pulse width followed by missing cycles waiting for the output voltage to fall back to the internal reference.  What looks like a low-frequency stability issue may be the beat frequency between the fixed frequency internal clock and the natural hysteretic response of the L-C running at minimum on-time.