LM5117 tolerance to switching spikes coupling to LO output pin

Hi

Usually, the ringing is not so big. Please refer Figure7 at http://www.ti.com/general/docs/lit/getliterature.tsp?literatureNumber=snoa543&fileType=pdf and measure the ripple again with a short ground ring. You have to measure the pin-to-pin voltage between LO pin and PGND pin.

Such a ringing can be minimized by increasing/adding  high-side gate resistor between HO and the gate of high-side NMOS switch.

Regards,

Hi Eric,

Thanks for the quick response.

Unfortunately, my measurement technique was as per Figure 7 and so I think the noise at the LO pin really is as bad as +/-7V.

Using your suggestion of adding a high-side gate resistor I can reduce the noise considerably, as detailed below:

Gate resistor         Noise at LO      Rise time at SW      Fall time at SW

0R                           +/-7.4V                9ns                            32ns

2R7                         +/-4.7V

4R7                         +/-3.8V

10R                         +/-2.4V

22R                         +/-1.1V                33ns                          52ns

At 22R, I estimate that I have increased the FET power dissipation by around 1.3Watts (calculated from the increased transition time). Given that the noise spike on the LO pin is only 20ns in duration (once per cycle with a switching frequency of 127kHz) how far do you think I need to go? What is the maximum spike amplitude at the LO pin that you would consider to be safe?

Best regards,

Gavin.

Hi

Absolute maximum rating of LO pin is VCC+0.3, -0.3V.

If you want to reduce more, you can add a small capaitor between the gate and source of low-side switch and/or between LO and PGND. Selecting higher Cgs MOSFET is another way you can try.

Normally, the noise at LO pin is not so big. I hope you can measure again with shorter ground lead and close to the IC.

Regards,

Hi Eric,

I am using an active probe (<1pF) with a ground lead length less than half an inch. The dimensions of the probe body do not allow for a shorter ground connection. The probe tip is within 60 thou of the LO pin and the ground connection is on the AGND pin of the chip (probe tip to ground connection measures 260 thou across the board).

I have discovered that the source of much of the problem is the inductance of the sense resistor. I am using an 8mOhm 1W resistor in a 2512 package. Whilst the ground end of the resistor is quiet, the other end has significant ringing. I can fix this by fitting a 100nF 0402 capacitor from the sense node to ground. As well as now meeting the abs max spec on the CS pin (I had not measured the ringing on this pin when I wrote my last post) this capacitor has significantly improved the ringing on the LO pin.

The solution I am hoping to go with is to fit the capacitor described above, use 10R in series with the gate of the high side FET and use 2R7 in series with the gate of the low side FET. This seems to work well and is efficient. However, it does not strictly meet the abs max spec on the LO pin.

There remains a small negative blip on the LO pin which peaks at -600mV. It is below -300mV for 3ns. I can make small improvements to this, but only at the expense of significant reduction in efficiency.

Please can you provide some additional insight into the reason for the abs max spec on the LO pin? For example, if the specified value was chosen to  prevent overheating of an internal clamp diode, then I am happy that the blip I am seeing has negligible thermal energy and so is not a problem. Please let me know your thoughts on this.

Best regards,

Gavin.