TPS65910A3A1 I2C Interface

Hi Paul,

I just got the answer to this myself. Here's what I found out:

The TPS65910A I2C is able to support I2C clock stretching. It will force the clock low after write access, waiting for access to be completed internally and similarly before read access, waiting for data to be available internally. It is suppose to prevent the master from driving the clock too early (starting a new access while the previous one is not completed or reading data while not yet available).

If the master does not support I2C clock stretching (such as the AM335x), it will need to give enough time between 2 consecutive clock cyles in those situations.

Thanks,

Fern