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TPS40170 start up issues

Ramnath Chandrachood
Prodigy 245 points
Other Parts Discussed in Thread: TPS40170

Hi I am using TPS40170 for my 48V input to convert it to 12V,16A circuit. When I run a spice simulations then I do not see any issues and I see vout correctly at 12V@16A but somehow on the board, I something different. I just get Vout 2.26V. It does not go more than 2.26V.

Here are my observations so far -

When turned on, Vout simply rises from 0V to 2.26V and then flattens out.  This Vout value, because of the FB voltage divider, will never get it to within a value that will allow the switcher to obtain a high PGOOD.
PGOOD is low indicating that there is a problem with the power regulation.  From the switcher's datasheet they state that PGOOD pin will be pulled low in the event of one of conditions are met:

• VVFB is not within the PGOOD threshold limits.
• Soft-start is active, i.e., SS pin voltage is below VSS,FLT,HIGH limit.
• An undervoltage condition exists for the device.
• An overcurrent or short-circuit fault is detected.
• An over-temperature fault is detected.

VVFB is measured at 0.116V and is not within the limits of approx. 527-670 mV.
Soft-start is also active because the SS pin voltage is below VSS,FLT,HIGH limit of 2.5V.  We measured the SS pin voltage to be around 0.42V.  This pin is actually oscillating when I looked on the oscilloscope.  It never reaches above 2.5V limit.  I believe the other three items are not the culprit at the moment.

So, we have two conditions that are being met for PGOOD to be low and need to figure out why this is the case.  Figure 34 in the switcher's datasheet show a normal PGOOD power on sequence and as this figure shows, VFB needs to reach its settling value between VOV and VUV, which it is not since Vout only goes from 0 to 2.26V on power up.


Please advice.

I have attached the layout and schematic for your reference.
power_48v-12v.zip
  • 0
    TI__Mastermind 35165 points

    Hi Ramnath,

    What is the voltage on the TRK pin? This could be also be keeping the SS and output voltage from rising further.

    Also what program is the layout done in. I'm not familiar with the .mdd file extension.

    Best Regards,
    Anthony

  • 0 in reply to Anthony F
    Prodigy 245 points

    Hi Anthony,

    Layout is in Allegro format, Actually .mdd file you can open in allegro. I just cut the power supply section from the main board (.brd) file and created a module file ( .mdd).

    Is there any reason that TRK pin is keeping voltage from rising further?

  • 0 in reply to Ramnath Chandrachood
    TI__Mastermind 35165 points

    If for some reason the TRK voltage is lower than the internal reference and SS voltage the TPS40170 will regulate FB to this instead.

    Could you also take a few screenshots with an oscilloscope of the turn on of the device? I would like to see the SW voltage, SS voltage and output voltage.

    Best Regards,
    Anthony

  • 0 in reply to Anthony F
    Prodigy 245 points

    Hi Anthony,

    Here are the pictures

    1. Vout

    2. Vsw

    3. Vss turn on

    4 Vss

    .

    Pictures.zip
  • 0 in reply to Ramnath Chandrachood
    TI__Mastermind 35165 points

    Hi Ramnath,

    Looking at the screenshots it appears the TPS40170 entering current limit hiccup mode. Most likely it is falsely triggering the SCP. To remove this issue the use of a snubber and series resistor to slow down the turn on the high-side FETs is recommended. The snubber is dependent on layout but the following link gives a good step by step process: http://www.ti.com/ww/en/analog/power_management/snubber_circuit_design.html. For the series resistors a 4.7 ohm is a typical value used in series with the high-side gate drive signal and with the bootstrap capacitor. Lastly I recommend trying to replace R23 with a 1Ω resistor. The voltage drop from the bias current has been known to falsely trip SCP if the resistance is too high.

    There are also some layout improvements which could help remove the issue. With higher input voltages this is important because the switching node will be changing from GND to the input voltage. It is most important to minimize the input current loop which is marked up in yellow in the image in the following link: http://e2e.ti.com/cfs-file.ashx/__key/communityserver-discussions-components-files/196/0121.High-current-loop-EVM.png. I could only find C38 on the layout and this is relatively far from the high-side and low-side FETs.

    I also noticed there are only 2x 10uF for the input capacitor. Is there some bulk capacitance elsewhere on the board? This seems small.

    Best Regards,
    Anthony

  • 0 in reply to Anthony F
    Prodigy 245 points

    Hi Anthony,

    I created the RC-snubber circuit the way that was mentioned in the link that you sent to me.  As you can see from the screenshots, Vsw does not have the ringing like it did before.  However, the high-side fet is still not switching the way it should (as compared to the simulation waveforms that you sent).  I have also included a look at Vss (soft-start pin).  It does not rise above 2.5 V like it needs to and also the waveform looks different this time around.  Please let me know any other modifications that you would like me to do.

    VSS snubber:


    VSW Snubber:






    Snapshot.zip
  • 0 in reply to Ramnath Chandrachood
    TI__Mastermind 35165 points

    Hi Ramnath,

    What snubber values did you end up with? Can you also show the SW pin more zoomed out so multiple pulses are visible?

    Can you please also try adding the series gate drive resistor and boot resistor? This will also help reduce ringing and avoid false tripping of the SCP.

    Lastly using the Compensation Calculator Tool located on the TPS40170 product page it appears the phase margin might be too low. Some recommended values from this tool targeting 60 degrees phase margin are R7=20k, R3=590, R11=2.74k, R12=1.05k, C17=2200pF, C20=15nF, and C22=470pF.

    Best Regards,
    Anthony

  • 0 in reply to Anthony F
    Prodigy 245 points

    Hi Anthony,

    I followed that RC snubber link you sent me they have a design example at the end that they follow.  I did the same steps they did to deduce what my R and C were.  I also used the oscilloscope to see how the values were affecting the ringing.  To find the capacitance that would cut the ringing period in half I started adding 10nF caps in parallel until I got to about half the period.  For this case it was just two (so 20nF) that made the period about twice as long.  Then from this Cs = 20nF value I calculated Cext and calculated the rest.  I used T = 1 us and thus Fring = 909 kHz.  These values will then give you your Ls.  From there you can get your Csnub and Rsnub values.  I ended up just using a 47nF cap in series with a 11 ohm resistor.

    I also added R7=20k, R3=590, R11=2.74k, R12=1.05k, C17=2200pF, C20=15nF, and C22=470pF as a new compensation values.I also have series gate drive resistor(4.7ohms) as well as boot resistor(4.7ohms) in series with boot capacitor.

    This rework still does not cause high side FET to start switching.

    Here are the few waveforms for your reference -

    Kindly Advice.


    Regards,


    Ram





    Power_Supply_Status.zip
  • 0 in reply to Ramnath Chandrachood
    Prodigy 245 points

    Interestingly I run the spice simulations, which runs absolutely fine. I do not see the hiccups on the simulations that I see on the board.

    I am not sure what could be causing this supply to fail..

  • 0 in reply to Ramnath Chandrachood
    TI__Mastermind 35165 points

    Hi Ramnath,

    This could be related to layout. Can you please try testing with a lower VIN to see if the performance improves? Lower input voltages can be less sensitive to layout.

    Also what type of capacitors are C38 and C40? Ceramics are recommended because they have low ESR and provide better bypass. If these are not ceramic, can you try adding some as close as possible to the high-side and low-side FETs?

    Best Regards,
    Anthony

  • 0 in reply to Anthony F
    Prodigy 245 points

    Hi Anthony,


    I have uploaded the new snapshots of all the pin status. Kindly check and let me know if you see something which is not right. Currently we have fixed the compensation network to have 60 degree of phase margin, boot resistor and snubber circuit is in place. 

    I wanted to ask you about the layout issue. Do you see anything particular in the layout that makes you think is a problem?

    I also observed very strange thing, I used the pot of 100K resistor  at R7 at the compensation network and if I increase the values of the pot then vout goes upto 6V.  Unfortunately at this pot value high side switching is not correct.  I will try to capture these waveforms and send you the status later.

    Kindly  me know your view on the current waveforms.

    Thanks,

    Ram

  • 0 in reply to Ramnath Chandrachood
    Prodigy 245 points

    As an update for your questions,


    All caps are ceramic caps. I tried to lower down the VIN but it did not help.

  • 0 in reply to Ramnath Chandrachood
    TI__Mastermind 35165 points

    Hi Ramnath,

    Thank you for the screenshots on each pin. The switching waveform and high-side gate drive are very odd.

    I now noticed the ILIM resistor of 191kΩ is very large. This puts the ILIM voltage well above the 300mV max Ilim pin voltage operating range. Can you try reducing this to 25kΩ? Based on the 16mΩ max Rdson of the low-side FET, with two of them in parallel a 25kΩ resistor sets the OC limit at approximately 28A typical.

    Best Regards,
    Anthony

  • 0 in reply to Anthony F
    Prodigy 245 points

    Hi Anthony,

    I changed ILIM resistor to 25K but did not observe any effect.

    So, Today I updated All the components to match with reference design from TI for 48VIN to 12V@20A output. I see slight improvement on high side switching but it is not good enough. I see the small pulse instead of spike on high side switching.

    I have uploaded few snaps for your reference.

    Regards,


    Ram

  • 0 in reply to Ramnath Chandrachood
    TI__Mastermind 35165 points

    Hi Ramnath,

    Good to see you have had some improvement.

    Is there only the 2 ceramic capacitors shown on the schematic and can you share the part number for them? This reference design uses an LC filter and many capacitors 100V X7R capacitors on the input. The layout also has very good bypass near the high-side and low-side FETs to minimize the input current loop. This was one thing which could be improved on your layout.

    By the way I also recommend reducing the file size of the oscilloscope screenshots so you can upload them directly to the forum. The internal TI firewall blocks mediafire and I had to wait until I was on my personal computer to view them.

    Best Regards,
    Anthony