LM5069 fails to latch off

okan durmaz

Other Parts Discussed in Thread: LM5069

Hello

LM5069-1 (latch off type) drives a gate capacitance of ~10000pF in my application. When I tried to put LM5069-1in current limit mode, it tries to drive the FET periodically besides latching off FET. Input voltage is normal within this period.

I checked the UVLO pin, which I also use for enabling is ok (above 2.5V).

Also I checked OVLO pin which drops 560mV levels and returns to its normal level.

I attached the gate and timer cap voltage measurements.

Max gate voltage is equal to input voltage

What is the reason for not latching off?

(I performed tests in CR mode.)

Thank you

over 12 years ago

0 okan durmaz over 12 years ago

Prodigy 30 points

0 Michael Hartshorne over 12 years ago in reply to okan durmaz

TI__Genius 13245 points

Hi Okan,

Can you post the schematic? If not, what is the value of your timer cap.? I am not clear on what is happening in these pictures.

So you are increasing the load current beyond the current limit, and you would expect the device would shut down and not start up again, true? It is possible that input noise could trigger a restart sequence. Is there a capacitor on VIN?

Regards,

Mike

0 okan durmaz over 12 years ago in reply to Michael Hartshorne

Prodigy 30 points

Hi Mike;

The value of timer cap is 47nF, I measured the input voltage and VIN of IC with an oscilloscope. There is no change.

0 Randy Whiteside over 12 years ago in reply to Michael Hartshorne

Prodigy 10 points

Hi Mike,

I am having a similar issue. However, I have a much simpler set up. I observed when the only fault being the Vin pin voltage drops below 8.3 volts the -1 part tries to reset just like the -2 part.

Is this normal and if it is how you do get it to just turn off.

Schematic is like page 20 datasheet fig 15

System power is 8 to 12V

R1= 10k

R2=100k

R3= open

R4= Gnd

Rs=10 mohms

Out C= 1100uf

Ct=0.22uf

0 Michael Hartshorne over 12 years ago in reply to Randy Whiteside

TI__Genius 13245 points

Hi Randy,

When the LM5069 input goes below 7.6V (8.0V max) the device goes into Power-on-Reset (see POR spec. in data sheet). During the reset time, the gate is pulled low. When it comes out of reset (VIN goes above 8.4V, 9.0V max), the device will go through the "insertion delay" period then begin to start up.

I wouldn't recommend operating below 9.0V, noise can easily trigger the device to go into the POR.

I hope this helps,

Mike

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LM5069 fails to latch off