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BQ2031 DV2031S2 EVAL CIRCUIT

Alex Hubbard-Palmer
Prodigy 50 points

Hi

Could some one please explain the operation of the circuit show below. It this taken from the DV2031S2 datasheet.

From what I see, It looks like a gate to source clamp for the Pfet, also incorporating a general gate drive interface.

If someone could explain in more detail how it operates that would be great, as I am not 100% clear the gate voltage clamping.

Thank You 

  • 0
    Prodigy 50 points

    Ok I have spent some time redrawing this section to make it more clear, and it seems quite straight forward now. Please correct me if I'm wrong.

    Q4 is the main gate pull down, R22 limits gate capacitance discharge current. R4 is Q4s pull up.

    R6 pulls up Q1, D2 drops 15V so to keep Vgs safe. Q2 + Q3 form a fast gate turn off through Q3.

    C4 lets through a current pulse to Q2 so to turn it on, when Q5 is switched.

    R8 limits D2 current.  R7 Holds off Q2.

    In the schematic Q5 does not have a base resistor. Is the MOD pin ok with is? is the design relying on R8 emitter resistor to limit base current?

     

    Thanks