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bq20z75 V1.60 DFETD set when current calibration.....

Kjell Ramberg
Expert 1375 points

Dear all,

I have experienced a problem for some PCB's when trying to do a pack current calibration. I have a setup according to SLUA404 page 283 and i have followed the calibration instructions given on page 201-202 in the same document carefully. 

When starting current calibration (2A through the 10 mOhm resistor) DFETD became set. With an AFE SC Dsg setting 12 the SCD bit was also set when starting current calibration, When changing the AFE SC Dsg to 72 SCD did not became set, - only the DFETD. I had to perform a 2673 1712 comand and a MAC 0041 command to get DFETD cleared. I increased the FET Fail Time from 5 to 10. That did not have any effect. The only way to avoid this was setting Fet Fail Time to 0 (disable).

I think I have seen others on the E2E describing a similar problem.

What could possible cause this problem ?

Best regards

Kjell

  • 0
    TI__Guru 73830 points

    Kjell

    The calibration routine takes over control of the FETs during current calibration. In addition, current offsets and gains are being adjusted which may result in faults. It is recommended to disable faults during calibration to prevent false faults from occurring. You can set the FET Fail Time to 0 until after calibration has been completed the false FET faults from occurring.

    Regards
    Tom

  • 0 in reply to ThomasCosby
    Expert 1375 points

    Tom,

    Thank you so much for your support. I will follow your advice and set FET Fail time to 0 as a rutine when doing the calibration to avoid any false faults.

    I really appreciate the forum and the technical support given by TI. This has helped us a lot when starting at scratch with no knowledge of all the "tips and tricks".

    Best regards

    Kjell