LM26484 Datasheet Discrepencies

Hi Ken,

Thank you for your input and deligent observations:

1. It meant to be sinking capability and you are absolute correct as it is open drain sourcing is dependent on one's external pull up limiting resistor.

2. The Flexible nPOR is derived from LP3907, you may view the details from DS therein. It is timer based not voltage threshold.  However it is "fault" conditions that will trigger the counting of time by asynchronous events and starting RC oscillators use for delays, so are not fast ns type response time.  There are two type of npor inherently, one is those technology wide used por and npor circuitry on all products for generating a system reset signal as the power of the system achieves logic operation voltage typical  for this is 1.25V or 1.5V, for example.  This inherent npor is logically gated with another reset signal that is base on fault conditions and circumstance as discussed in above.  So either of the those events could manifest a system reset signal.  The DS could have been better in presenting this not so obvious 'feature'.  My apology.

3.Please advise what  was observed given Vin was in normal operating range and Ven=0V  such that the switcher is disabled.

4.Absolute rating for Vin is stated for reliability reason, which is not what you sought.  The operating rating of 3.0V to 5.5V is referenced. which gives you one data point at 3/0V.  The switcher should be able to operate at below 3V, but the DS makes no warranty of that. To check the so called absolute , presumably lowest voltage, that the buck may still operate, one may derive that emprically with the qualification of Vout, loading, temperature, etc. should be better determined.  I suspect that may be why it is not shown because of the variables.  Even if one finds a combination which allows the switcher to operate the a certain low Vin figure, Marketing may also not like to lock in such a figure on DS, which can become a pitting on merits among competitions.

5.This is an application issue we have not encountered, as the part is used in Big volume with automotive and industrial applications.  We are very much interested in learning your application details.  You may sent in the "fried" device for us to analyze. So how may systems has been assembled/produced and the pppm of this phenomenon?  Is this fast toggling a stress test or normal application demands this action sequence?  The switchers have soft start so they should be inrush protected.

However can you describe and monitor with RF technique the toggling of the Enables.  If the inputs are not directly and well controlled toggled, it may go below ground level as in very fast edge rate transition and /or long routing such that Ldi/dt can turn on normally  reverse biased PN junctions.  Can you duplicate this phenomenon readily and perhaps issue us setup to check.  By the way where are you located? Please email me at kern.wong@ti.com so I can respond to your queries directly, but do continue on with the E2E as others can benefit from our discussion.  Thank you.

Regards,

Kern

Hello Ken,.

I checked on a couple of  LM26484 EVBs and the EN pin functions do take the buck outputs to 0V when disabled with no loading.  What are your observations?  Are you performing the check on our EVB?  Be certain that the EN and Not the Vin pins are use as they are located close together one might inadvertently exercise the other mistakenly.  In that case it may present a similar scenario that you reported.

Regards,

Kern

Dear Kern,

Many thanks. I'm certain it's only the EN pin.

When the EN pin is logic low, the SW1 & SW2 outputs are OFF. Therefore, in the EVBs the outputs caps will eventually discharge to 0V. But in most applications, there will be current leaks through logic body diodes,etc, so the voltage at SW1 & SW2 may be kept at 2.4-2.6V. If the NMOS is turned on as described in the datasheet, it should actively sink the SW1 & SW2 to ground.

Maybe you can kindly try to have the outputs of the EVB tied to another supply of 2.5V via a 1K resistor (to simulate actual applications) and then put to low the EVB's EN pin. You may be able to see that the SW1 & SW2 high side do turn off but the low side is also off and does not actively sink the SW1 & SW2 to ground to discharge the residual or parasitic voltage on the outputs. In this setup, if the EN pin is cycled quickly, the latch-up tends to be observed.

I'm travelling now and my apologies for my sluggish response. Greatly appreciate your kind assistance.

Hi Ken,

I see what you mean.  Your application is a bit different from the intended flow.    The pull down is intended to "bleed" out the residual charge remained in the load cap.  For most applications when a power source is shut down, the system likes to 'see' its goes to 0V, the faster the better. In your particular case it appears the required sink may be pretty hefty, in the orders of mA or hundreds of mA which the part is not meant to perform.  In disable the part does sink some current uA not mA. I tied a 1K from SW1out@ 1.8V and feed i to SW2 out powered down the IR drop was tens of mV, Use a 1Mohm it dropped the 1.8V to ~10mV.  So ouput in disable sinks very modest current to discharge Cout.   As to why no hard and heavy driving of the lower side at disable? I think there are +&- current & voltage sensing,  driver, comparators, and monitoring circuits are involved and in disable mode they are inactivated to save power and prevent mishaps.  To make it achieve your goal in theory it will work, but for reliability or unusually event when section is debiased it might be better if an extra  internal nmos was used like a "true shutdown" outputs used (and then there is the economic issue because to handle such a large sink the FET has to be relative large- that is why even tru shut downs  don't typically sink much current either). 

Curiously what is the buck driving down stream that when not operating there is a such a "back" blow of current into the pmu?  You might have to arrest the manifestation down there where the culprit exists.   Let me know if I may be of help further.

Regards,

Kern

1. It was stated in the datasheet when in Shutdown ( assumed as EN1 & EN2 are logic low ), the SW NMOS will be turned on to discharge the output caps. The NMOS switch should be if I'm not mistaken is the the syncronous rectifier NMOS of the buck and should be able to sink quite a lot of current.

It was more from the datasheet which we assumed that the NMOS will be able to discharge the output therefore we did not take any additional external fets to purposely discharge the external circuits.

Since the Switcher internal power nmos was logically able to perform such a feature, we did not doubt the datasheet and designed our circuit around it.

Really appreciate your help. The real problem is the latch up phenomenon that is killing our LM26484 now. In the presence of external voltages at SW1 or SW2, rapid cycling of the EN pins have been observe to latch up the PMOS and NMOS simultaneously, leading to the IC frying itself.

Once back in my lab this weekend, I'll send you some waveforms of the latched up state.

Regards. Ken.