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TPS6306x Land Pattern

Other Parts Discussed in Thread: TPS63060

Hello,

After ordering the TPS63060 EVM and testing for my application, it seems to work alright. Now it's time to add this part to our device library in Eagle EDA layout editor.

However, the land pattern on the EVM user's guide and the device's datasheet is NOT the same! There are 4 PGND pins on each side of the IC in the datasheet, but the EVM shows a land pattern that has 2 PGND pins on each side.

Which one is correct? Any advice is greatly appreciated.

Thank you,

  • The very end of the D/S contains the thermal pad drawing and a recommended board layout.  These are the authority   There are also CAD drawings available on the product page at the very bottom.

  • Hi Chris,

    Thank you for your quick response.

    I have always assumed exactly what you stated: that the end of the datasheet is the authority to device info - including IC footprints and land patterns.

    Still, why is it that on my TPS63060 EVM (which is populated with the EXACT same device I am making a land pattern for), I can clearly see 2 PGND pins on each side of the IC, yet the datasheet says it has 4 PGND pins on each side? What am I missing here?

    I can't make a land pattern for this device based on info in the datasheet, when the TPS63060 EVM is performing just fine with a different land pattern (a fact that I can physically see).

    Thank you again,

  • It's up to you to decide how to make the land pattern for your product but TI's recommendation is at the end of the D/S.  Some companies don't follow this due to their own company's rules about such matters.  Or their manufacturer may ask them to use a different setup to have better assembly success.  Regarding the EVM, we might be required to do such things ourselves or we may have just drawn the footprint wrong.  The fact that it's working on the EVM is expected.  A difference like that would most likely show up as an issue during the assembly of the PCB, not in the IC's performance.

  • Thank you Chris.

    My question about the land pattern really stems from the fact that the TPS6306x datasheet (http://www.ti.com/lit/ds/symlink/tps63060.pdf) shows its pinout having 4 ground pins on each side (see page 4 in the DS), but the TPS63060 populated on the EVM clearly has 2 ground pins on each side. Is this an error in the datasheet?

  • Those are not really "pins" in the usually meaning.  The IC "pins" are numbered 1 thru 10 (10 pin SON package).  Those are considered "optional exposed metalized feature", see Note E on page 28 of the datasheet.  They may or may not be present depending on the lead frame supplier.  They are just extensions of the exposed thermal pad, which is internally connected to PGND.

  • Thank you for your reply.

    I get that they are not "pins" in the usual meaning, But my original question remains unanswered. I just want to know, for sure (without any reasonable doubt), how many of these exposed ground pins there are (on each side of the TPS6306x IC).

    AND which land pattern should I be using in my PCB? Because it sounds like the one at the end of the datasheet is wrong. Thank you.

  • Per my first reply, the D/S is the authority on these matters.  Follow its guidelines.

  • Thanks Chris, and also John, for your replies. 

    But it sounds like I'm not going to get an answer to my question: how many "ground pins" (connecting to the thermal pad under the device) are on each side of the IC?

    So I am just going to buy a few of these ICs (from Digi-Key or Mouser) and just check myself. I will post the answer here when I receive them, because if there are 2 ground "pins" on each side, then the datasheet's land pattern is wrong and may need some kind of revision or clarification.

  • As i stated earlier, they are not "pins" just extensions of the exposed thermal pad.  If you follow the recommended footprint, you should not have any problems whether there are 2, 4 or none on each side.  They are optional features which are dependent on the actual supplier for the lead frame.

  • Thank you John.

    I received the ICs earlier today, and I did verify that its footprint is exactly as the datasheet says, which I will use as a reference for my design.

    But it should be noted that the EVM's land pattern for the IC shows 2 ground extensions (on each side of the IC) of the exposed thermal pad - versus the 4 shown in the devices datasheet. That was where my confusion arose.

    Thank you again, John and Chris, for all your help and suggestions.