UCC2897 / Pulse skipped at high Vin and no load

Satoshi-san,

Each time the main switch fires no matter how short a small amount of energy is transfered to the secondary. If there is no load this translates into an increase on voltage on the output. If the amount of load on the secondary is less than the energy being transfered the output voltage then to maintain the voltage within the tolerances of the control circuit the converter starts to skip pulses. that is what you are most likely seeing.

John

Hi John-san,

Thank you for your response.

I understand what you commented that the pulses is skipped when the output voltage is maintained within the tolerances at no load condition. But can we see that operation from the description in datasheet? I could not find the description that explain the operation like that.

Best Regards,

Sonoki

Satoshi-san,

I don't believe no load operation is touched on in the data sheet and if it is the converter they are using has sync rectifiers on the output which prevents the output voltage build up that diodes allow.

The discription i furnished is what is happenning and the data sheet specifies 0% minimum duty cycle (pulse skipping) and it specifies a PWM offset of 0.43 to 0.60 volts so any time the FB signal is below the (PWM offset x  5) there will be no pulses.

John

Hi John-san,

Our customer commented that the FB voltage is not under 2.5V when they confirmed pulse skipping at no load condition. Is this operation normal in this device?

Best Regards,

Sonoki

Satoshi-san,

Take a look at the FB pin using tip and barrel and no bandwidth limiting measurement technique. The high end of the PWM offset is 0.61 V and 5 times that  is 3.05 volts.

Does the waveform extend below 3.05 volts?

Send me scope images of the FB pin and the CS pin during pulse skipping.

John

Hi John-san,

I will request customer to take waveform on FB pin and CS pin.

Please let me share it with you when I get it.

Best Regards,

Sonoki

Hi John-san,

Sorry for my delayed response but I'm waiting for the waveform you requested from customer.

And now I have received one question from them for your comments. You commented "The high end of the PWM offset is 0.61 V and 5 times that  is 3.05 volts." but we do not understand this calculation that is 0.61 V and 5 times. Can you explain about it?

Best Regards,

Sonoki

Hi Satoshi-san,

Look at the block diagram on page 6 of the specification. The CS signal from pin 9 to the comparator shows a 0.5 V level shift.  There for is the CS signal is at zero volts the signal on the positive side of thecomparator is at +0.5 volts.

The signal from the FB pin goes through a unity gain amplifier into a resistor series of 4R and R. The junction of the 4R and R series is connected to the negative input. So with zero volts on pin 9 the voltage on the FB pin would have to be 5 times the 0.5 volt offset to have the negative input equal to the positive input, or 2.5 volts.

But looking at the data sheet page 5 under the PWM section it indicates that the 0.5 volt offset can be as high 0.61 volts which means that the maximum voltage on the FB pin to get no pulses may be as high as 3.05 volts but on another IC it may be as low as 0.43 V x 5 or 2.15 volts. The customer has to design for the total range of variations.

Regards,

John